<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_sqrt.vhd sqrt.vhd post_norm_sqrt.vhd comppack.vhd fpu.vhd ***For simulation **** To run the simulation read readme.txt in folder test_bench.
標(biāo)簽： vhd post_norm_addsub pre_norm_addsub Floating
上傳時(shí)間： 2014-01-18
上傳用戶(hù)：czl10052678
This example application is a collection of Flash Lite do s and don ts from the usability point of view. The application contains real examples and animations of static examples that help you to see problematic issues in real life on a Nokia device. The application is optimized for devices with the resolution 170 x 208 pixels used in portrait mode. This example application is closely related to the document Flash Lite: Visual Guide, and it is highly recommended to read the document before going through this example.
標(biāo)簽： application collection usability example
上傳時(shí)間： 2015-10-05
上傳用戶(hù)：trepb001
NAME: u2440mon.c DESC: u2440mon entry point,menu,download HISTORY: Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2410X. Mar.27.2002:purnnamu: DMA is enabled. Apr.01.2002:purnnamu: isDownloadReady flag is added. Apr.10.2002:purnnamu: - Selecting menu is available in the waiting loop. So, isDownloadReady flag gets not needed - UART ch.1 can be selected for the console. Aug.20.2002:purnnamu: revision number change 0.2 -> R1.1 Sep.03.2002:purnnamu: To remove the power noise in the USB signal, the unused CLKOUT0,1 is disabled.
標(biāo)簽： 2440 mon download purnnamu
上傳時(shí)間： 2016-05-12
上傳用戶(hù)：wff
The FastICA package is a free (GPL) MATLAB program that implements the fast fixed-point algorithm for independent component analysis and projection pursuit. It features an easy-to-use graphical user interface, and a computationally powerful algorithm.
標(biāo)簽： fixed-point implements algorithm FastICA
上傳時(shí)間： 2014-08-17
上傳用戶(hù)：yy541071797
For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while efficiently managing data flow through the parallel pipelines of these processes.
標(biāo)簽： floating-point implementation developers functions
上傳時(shí)間： 2013-12-16
上傳用戶(hù)：tonyshao
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs.
標(biāo)簽： TMS 320 fixed-point processor
上傳時(shí)間： 2013-12-27
上傳用戶(hù)：宋桃子
java聯(lián)網(wǎng)斗地主源代碼 這是紙牌游戲斗地主,算法完整,可以單機(jī),網(wǎng)絡(luò)連線(xiàn)玩.-This is the card game that point, the algorithm integrity, a stand-alone, playing to connect to the network.
標(biāo)簽： algorithm integrity the point
上傳時(shí)間： 2013-12-22
上傳用戶(hù)：aig85
This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
標(biāo)簽： applications development hardware paper
上傳時(shí)間： 2013-12-21
上傳用戶(hù)：jichenxi0730
Fast Fourier Transform power point The rectangular window introduces broadening of any frequency components [`smearing鈥? and sidelobesthat may overlap with other frequency components [`leakage鈥?. 鈥he effect improves as Nincreases 鈥owever, the rectangle window has poor properties and better choices of wncan lead to better spectral properties [less leakage, in particular] 鈥搃.e. instead of just truncating the summation, we can pre-multiply by a suitable window function wnthat has better frequency domain properties. 鈥ore on window design in the filter design section of the course
標(biāo)簽： rectangular introduces broadening Transform
上傳時(shí)間： 2017-03-25
上傳用戶(hù)：change0329
A Convex Hull is the smallest convex polygon that contains every point of the set S. A polygon P is convex if and only if, for any two points A and B inside the polygon, the line segment AB is inside P. One way to visualize a convex hull is to put a "rubber band" around all the points, and let it wrap as tight as it can. The resultant polygon is a convex hull.
標(biāo)簽： polygon S. the contains
上傳時(shí)間： 2013-12-23
上傳用戶(hù)：it男一枚
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