Analog Device ARM-7 系列之 ADuC_7024 Evaluation Board 內(nèi)多個(gè)學(xué)習(xí)范例全都是基于 Keil 工程版的 范例,附 ADuC_7024 Evaluation Board 原理圖,而范例內(nèi)容如下: 1.ADC 2.Comp 3.DAC 4.FlashEE 5.FuncRam 6.INT 7.Mics 8.PLA 9.PULSE 10.PWM 11.S&C 12.TimerTrig 13.UART 14.Varplace
標(biāo)簽： ADuC 7024 Evaluation Evaluati
上傳時(shí)間： 2016-01-01
上傳用戶：lo25643
A new cable fault location method based on wavelet reconstruction is proposed. In this method the difference between the currents of faulty phase and sound phase under the high voltage PULSE excitation is used as the measured signal and is decomposed in multi-scale by wavelet transform, then reconstructed in single scale. Comparing with traditional fault location method by travelling wave, the presented method will not be interfered by the reflected wave from the branch joint of cables or from other positions where the impedances are not matched and not be influenced by fault types, otherwise, the reflected waves can be recognized even the faulty position is near to the measuring terminal, at the same time, the influence of the wave speed uncertainty can be reduced. The correctness of the proposed method is proved by simulation results.
標(biāo)簽： method reconstruction location proposed
上傳時(shí)間： 2016-02-04
上傳用戶：maizezhen
A digital fi‘equeney meter designed with FPGA development software Q-~us 11 is introduced．The 1 Hz—l MHz input measured PULSE signals of the digital ii‘equency meter can be used for measuring frequency，period，PULSE width and duty ratio，etc．The test results stably display O71 3 seven—segment numeric tubes，and the measuring ranges may be switched over automatically．The measuring error is equal to or less than 0．1％．
標(biāo)簽： development introduced designed software
上傳時(shí)間： 2016-04-09
上傳用戶：stewart·
This example demonstrates the use of the ADC block and PWM blocks. The generated DSP code produces the PULSE waveform whose duty cycle is changing as the voltage applied to ADC input changes. The waveform period is kept constant.
標(biāo)簽： demonstrates the generated produces
上傳時(shí)間： 2016-05-17
上傳用戶：sjyy1001
The PWM_1 project is a simple program for the STM32F103RBT6 using Keil MCBSTM32 Evaluation Board and demonstrating the use of PWM (PULSE Width Modulation) with Timer TIM4.
標(biāo)簽： Evaluation project program MCBSTM
上傳時(shí)間： 2013-12-25
上傳用戶：familiarsmile
s3c2410提供了5個(gè)16位的Timer（Timer0~Timer4），其中Timer0~Timer3支持PULSE Width Modulation—— PWM（脈寬調(diào)制 ）。Timer4是一個(gè)內(nèi)部定時(shí)器（internal timer），
上傳時(shí)間： 2013-12-16
上傳用戶：569342831
This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian PULSE.
標(biāo)簽： differential bandwidth simulates system
上傳時(shí)間： 2014-01-03
上傳用戶：784533221
Modify the Gray-coded modulation example (COMMDOC_GRAY) so that it uses a pair of square root raised cosine filters to perform PULSE shaping and matched filtering at the transmitter and receiver, respectively.
標(biāo)簽： COMMDOC_GRAY Gray-coded modulation example
上傳時(shí)間： 2017-01-08
上傳用戶：zhangzhenyu
Tiny Planet is small device connected to a GSM cell phone. When the mobile receives a predefined SMS (text message), like "Activate burglar alarm" or "Start backup pump", the circuit automatically recognizes it as a command, and switches the output port accordingly. Besides switching the port on or off, the user can PULSE it for a short period (e.g. 鈥淩eboot remote server鈥?.
標(biāo)簽： predefined connected receives Planet
上傳時(shí)間： 2017-05-17
上傳用戶：fanboynet
摘 要 文章以空間監(jiān)控系統(tǒng)為背景,深入研究了JPEG圖像壓縮標(biāo)準(zhǔn)的實(shí)現(xiàn)方法,并基于FPGA對其進(jìn)行了實(shí)現(xiàn)和優(yōu)化。文中給出了詳細(xì)的實(shí)現(xiàn)方法和優(yōu)化過程,測試表明達(dá)到了很好的效果。 簡單介紹了有損靜態(tài)圖像壓縮當(dāng)前有兩種比較流行的標(biāo)準(zhǔn)JPEG和JPEG2000。說明了用JPEG方法壓縮的原因。 介紹JPEG基本原理：JPEG對灰度圖像的壓縮處理過程主要包括:圖像分割,離散余弦變換(DCT),量化(Quantization),“Z”形排序(Zigzag Scan),差分脈沖編碼調(diào)制(Differential PULSE Code Modulation,DPCM)對直流系數(shù)(DC),行程長度編碼(Run-Length Encoding,RLE)對交流系數(shù)(AC),霍夫曼(Huffman)編碼等。 JPEG標(biāo)準(zhǔn)的特點(diǎn)是離散余弦變換。 比較詳細(xì)介紹壓縮系統(tǒng)的構(gòu)成和實(shí)現(xiàn)。實(shí)現(xiàn)提及步驟， JPEG壓縮模塊設(shè)計(jì)和編碼模塊實(shí)現(xiàn)細(xì)節(jié)。
標(biāo)簽： JPEG FPGA 實(shí)現(xiàn)方法 監(jiān)控系統(tǒng)
上傳時(shí)間： 2013-12-25
上傳用戶：410805624
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