為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標(biāo)簽： xilinx SRAM VHDL ZBT
上傳時(shí)間： 2013-11-24
上傳用戶：31633073
為了提高蒙特卡羅模擬分析的效率，設(shè)計(jì)了一種以Platform Symphony為基礎(chǔ)的云計(jì)算平臺(tái)，并對(duì)平臺(tái)進(jìn)行了擴(kuò)展和集成，詳細(xì)論述了實(shí)現(xiàn)的過(guò)程以及關(guān)鍵技術(shù)。通過(guò)實(shí)驗(yàn)表明，該平臺(tái)能夠進(jìn)行高性能計(jì)算，輸出的結(jié)果精確，是實(shí)現(xiàn)蒙特卡羅模擬分析的實(shí)用工具。
上傳時(shí)間： 2013-12-22
上傳用戶：kangqiaoyibie
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時(shí)間： 2013-10-26
上傳用戶：yuzsu
為提升虛擬儀器傳輸速率與實(shí)時(shí)性能，擴(kuò)展監(jiān)測(cè)范圍，在VC的軟件平臺(tái)上設(shè)計(jì)了一種全功能虛擬示波器。與傳統(tǒng)虛擬示波器相比，該系統(tǒng)采用嵌入式系統(tǒng)完成信號(hào)采集，采用工業(yè)以太網(wǎng)為傳輸介質(zhì)，通過(guò)線性插值算法和多線程編程思想，實(shí)現(xiàn)波形顯示、參數(shù)計(jì)算、頻譜分析以及波形存儲(chǔ)及回放功能。實(shí)驗(yàn)結(jié)果表明，該虛擬示波器可以實(shí)現(xiàn)20 kHz采樣頻率下的波形精確顯示，達(dá)到預(yù)期的各項(xiàng)指標(biāo)。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
標(biāo)簽： 以太網(wǎng) 虛擬 波器設(shè)計(jì)
上傳時(shí)間： 2013-11-25
上傳用戶：wbwyl
User ManualRev. 1.2SmartRF® CC2420DK: Packet Sniffer for IEEE 802.15.4 and ZigBee Table of contents1 INTRODUCTION...............................................................................................31.1 HARDWARE PLATFORM.......................................................................................31.2 SOFTWARE.........................................................................................................32 USER INTERFACE..........................................................................................42.1 MENUS AND TOOLBARS.......................................................................................62.2 SETUP................................................................................................................62.3 SELECT FIELDS...................................................................................................72.3.1 Tips............................................................................................................72.4 PACKET DETAILS.................................................................................................72.5 ADDRESS BOOK..................................................................................................92.5.1 Tips............................................................................................................92.6 DISPLAY FILTER................................................................................................102.7 TIME LINE.........................................................................................................103 HELP....................................................................................................................114 TROUBLESHOOTING..................................................................................125 GENERAL INFORMATION........................................................................135.1 DOCUMENT HISTORY........................................................................................135.2 DISCLAIMER......................................................................................................135.3 TRADEMARKS...................................................................................................136 ADDRESS INFORMATION........................................................................14
標(biāo)簽： 數(shù)據(jù) 分析儀 說(shuō)明書(shū)
上傳時(shí)間： 2014-01-14
上傳用戶：zhangyi99104144
Then use Freescale’s InteractiveDevelopment Tool Ecosystem todesign a development processthat fulfills your specific needs.
標(biāo)簽： 飛思卡爾 開(kāi)發(fā)工具
上傳時(shí)間： 2013-10-26
上傳用戶：朗朗乾坤
This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
標(biāo)簽： Virtex TEMAC XAPP 1023
上傳時(shí)間： 2013-11-11
上傳用戶：saharawalker
This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
標(biāo)簽： XAPP 996 雙處理器 參考設(shè)計(jì)
上傳時(shí)間： 2013-10-29
上傳用戶：旭521
The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
上傳時(shí)間： 2013-10-26
上傳用戶：agent
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