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PowerPC

PowerPC（英語：PerformanceOptimizationWithEnhancedRISC–PerformanceComputing，有時簡稱PPC）是一種精簡指令集（RISC）架構的中央處理器（CPU），其基本的設計源自IBM的POWER（PerformanceOptimizedWithEnhancedRISC；《IBMConnect電子報》2007年8月號譯為“增強RISC性能優化”）架構。POWER是1991年，Apple、IBM、Motorola組成的AIM聯盟所發展出的微處理器架構。PowerPC是整個AIM聯盟平臺的一部分，并且是唯一的一部分。但蘋果電腦自2005年起，將旗下電腦產品轉用IntelCPU。

MPC106 PCI橋/存儲器控制器硬件規范說明

The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29

標簽： MPC 106 PCI 存儲器

上傳時間： 2013-11-04

上傳用戶：as275944189
MPC7400 Part Number Speci&THOR

MPC7400 Part Number SpeciÞcationThis document describes part number speciÞc changes to recommended operating conditions and revised electrical speciÞcations,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcations.SpeciÞcations provided in this Part Number SpeciÞcation supersede those in theMPC7400 Hardware SpeciÞcationsdated 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcations not addressed herein are unchanged. This document isfrequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version.Note that headings and table numbers in this data sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcation.

標簽： Number Speci 7400 Part

上傳時間： 2014-12-28

上傳用戶：huyahui
MPC7400l零件號碼規范說明

This document describes part number speciÞc changes to recommended operating conditions and revised electrical speciÞcations,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcations.SpeciÞcations provided in this Part Number SpeciÞcation supersede those in theMPC7400 Hardware SpeciÞcationsdated 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcations not addressed herein are unchanged. This document isfrequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version.Note that headings and table numbers in this data sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcation.Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Table B.

標簽： 7400l 7400 MPC 零件

上傳時間： 2013-11-19

上傳用戶：qiaoyue
XAPP806 -決定DDR反饋時鐘的最佳DCM相移

This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

標簽： XAPP 806 DDR DCM

上傳時間： 2013-10-15

上傳用戶：euroford
XAPP719 -利用USR_ACCESS寄存器實現PowerPC高速緩存配置

The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.

標簽： USR_ACCESS PowerPC XAPP 719

上傳時間： 2013-11-13

上傳用戶：我累個乖乖
DS306-PPC405 Virtex-4 Wrapper

The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.

標簽： Wrapper Virtex 306 405

上傳時間： 2014-12-05

上傳用戶：flg0001
XAPP482 - MicroBlaze Platform Flash,PROM 引導加載器和用戶數據存儲

　　本應用指南講述一種實用的 MicroBlaze™ 系統，用于在非易失性 Platform Flash PROM 中存儲軟件代碼、用戶數據和配置數據，以簡化系統設計和降低成本。另外，本應用指南還介紹一種可移植的硬件設計、一個軟件設計以及在實現流程中使用的其他腳本實用工具。　　簡介許多 FPGA 設計都集成了使用 MicroBlaze 和 PowerPC™ 處理器的軟件嵌入式系統，這些設計同時使用外部易失性存儲器來執行軟件代碼。使用易失性存儲器的系統還必須包含一個非易失性器件，用來在斷電期間存儲軟件代碼。大多數 FPGA 系統都在電路板上使用 Platform FlashPROM (在本文中稱作 PROM)，用于在上電時加載 FPGA 配置數據。另外，許多應用還可能使用其他非易失性器件(如 SPI Flash、Parallel Flash 或 PIC)來保存 MAC 地址等少量用戶數據，因此導致系統電路板上存在大量非易失性器件。

標簽： MicroBlaze Platform Flash XAPP

上傳時間： 2013-10-13

上傳用戶：hakim
XAPP807-封裝最小的三態以太網MAC處理引擎

The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.

標簽： XAPP 807 MAC 封裝

上傳時間： 2013-10-26

上傳用戶：yuzsu
XAPP996-雙處理器參考設計套件

This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.

標簽： XAPP 996 雙處理器參考設計

上傳時間： 2013-10-29

上傳用戶：旭521
VxWorks6.x中的ML403嵌入式開發平臺

The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.

標簽： VxWorks 403 ML 嵌入式

上傳時間： 2013-10-26

上傳用戶：agent

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