This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
WP369可擴(kuò)展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
標(biāo)簽： 369 WP 擴(kuò)展式 處理平臺
上傳時(shí)間： 2013-10-18
上傳用戶：cursor
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-10-09
上傳用戶：evil
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時(shí)間： 2013-10-20
上傳用戶：dave520l
這個(gè)軟件需要你的本機(jī)操作的。其他機(jī)器是算不出來的！ 就是說 一臺電腦只有一個(gè)注冊碼對應(yīng)！ 這里有個(gè)辦法： MULTISIM2001安裝方法： 一：運(yùn)行SETUP.EXE安裝。在安裝時(shí)，要重新啟動計(jì)算機(jī)一次。 二：啟動后在“開始>程序”中找到STARTUP項(xiàng)，運(yùn)行后，繼續(xù)進(jìn)行安裝，安裝過程中，第一次要求輸入“CODE"碼時(shí)， 輸入“PP-0411-48015-7464-32084"輸入后，會提示"VALID SERIAL NUMBER FOR MULTISIM 2001 POWER-PRO." 按確定，又會出現(xiàn)一個(gè)“feature code”框，輸入“FC-6424-04180-0044-13881”后， 在彈出的對話框中選擇“取消”，一路確定即可完成安裝。 三：1.運(yùn)行VERILOG目錄內(nèi)的SETUP安裝 2.運(yùn)行FPGA目錄內(nèi)的SETUP安裝 3.將CRACK目錄內(nèi)的LICMGR.DLL拷貝到WINDOWS系統(tǒng)的SYSTEM 目錄內(nèi) 4.并將VERILOG安裝目錄內(nèi)的同名文件刪除 5.將SILOS.LIC文件拷到VERILOG安裝目錄內(nèi)覆蓋原文件，并作如下編輯： 6.將“COMPUTER_NAME”替換為你的機(jī)器名 7.將“D:\MULTISIM\VERILOG\PATH_TO_SIMUCAD.EXE”替換為你的 實(shí)際安裝路徑。如此你便可以使用VERILOG了。 四：安裝之后，運(yùn)行MULTISIM2001,會要求輸入“RELEASE CODE",不用著急， 記下“SERIAL NUMBER"和“SIGNATURE NUMBER", 使用CRACK目錄內(nèi)的注冊器“MULTISIM KEYGEN.EXE" 將剛才記下的兩個(gè)號碼分別填入后， 即可得到"RELEASE CODE", 以后就可以正常使用了。 五：接下來運(yùn)行 database update目錄中的幾個(gè)文件， 進(jìn)行數(shù)據(jù)庫合并即可。祝你成功！！ 六：啟動MULTISIM2001時(shí)候的注冊碼 1： PP-0411-48015-7464-32084 2： 37506-86380 3:的三個(gè)空格 1975 2711 4842 里面包含了：Multisim2001漢化破解版、Multisim.V10.0.1.漢化破解版圖解 解壓密碼：www.pp51.com
標(biāo)簽： Multisim 2001 漢化破解版 免費(fèi)下載
上傳時(shí)間： 2013-11-16
上傳用戶：天空說我在
研究一種基于TMS320F28335 DSP（Digital Signal Processor）的全數(shù)字飛行器控制系統(tǒng)的硬件設(shè)計(jì)，分析了其結(jié)構(gòu)組成：主控制器電路、舵面位置檢測電路和通訊等硬件電路設(shè)計(jì)。經(jīng)過多次試驗(yàn)調(diào)試，所設(shè)計(jì)的硬件系統(tǒng)可以滿足飛行器性能要求。
標(biāo)簽： 飛行器 舵機(jī) 控制系統(tǒng) 硬件設(shè)計(jì)
上傳時(shí)間： 2013-10-10
上傳用戶：z1191176801
12864液晶時(shí)鐘顯示程序 LCD 地址變量 ;**************變量的定義***************** RS BIT P2.0 ;LCD數(shù)據(jù)/命令選擇端(H/L) RW BIT P2.1 ;LCD讀/寫選擇端(H/L) EP BIT P2.2 ;LCD使能控制 PSB EQU P2.3 RST EQU P2.5 PRE BIT P1.4 ;調(diào)整鍵(K1) ADJ BIT P1.5 ;調(diào)整鍵(K2) COMDAT EQU P0 LED EQU P0.3 YEAR DATA 18H ;年,月,日變量 MONTH DATA 19H DATE DATA 1AH WEEK DATA 1BH HOUR DATA 1CH ;時(shí),分,秒,百分之一秒變量 MIN DATA 1DH SEC DATA 1EH SEC100 DATA 1FH STATE DATA 23H LEAP BIT STATE.1 ;是否閏年標(biāo)志1--閏年，0--平年 KEY_S DATA 24H ;當(dāng)前掃描鍵值 KEY_V DATA 25H ;上次掃描鍵值 DIS_BUF_U0 DATA 26H ;LCD第一排顯示緩沖區(qū) DIS_BUF_U1 DATA 27H DIS_BUF_U2 DATA 28H DIS_BUF_U3 DATA 29H DIS_BUF_U4 DATA 2AH DIS_BUF_U5 DATA 2BH DIS_BUF_U6 DATA 2CH DIS_BUF_U7 DATA 2DH DIS_BUF_U8 DATA 2EH DIS_BUF_U9 DATA 2FH DIS_BUF_U10 DATA 30H DIS_BUF_U11 DATA 31H DIS_BUF_U12 DATA 32H DIS_BUF_U13 DATA 33H DIS_BUF_U14 DATA 34H DIS_BUF_U15 DATA 35H DIS_BUF_L0 DATA 36H ;LCD第三排顯示緩沖區(qū) DIS_BUF_L1 DATA 37H DIS_BUF_L2 DATA 38H DIS_BUF_L3 DATA 39H DIS_BUF_L4 DATA 3AH DIS_BUF_L5 DATA 3BH DIS_BUF_L6 DATA 3CH DIS_BUF_L7 DATA 3DH DIS_BUF_L8 DATA 3EH DIS_BUF_L9 DATA 3FH DIS_BUF_L10 DATA 40H DIS_BUF_L11 DATA 41H DIS_BUF_L12 DATA 42H DIS_BUF_L13 DATA 43H DIS_BUF_L14 DATA 44H DIS_BUF_L15 DATA 45H FLAG DATA 46H ;1-年，2-月，3-日，4-時(shí)，5-分，6-秒，7-退出調(diào)整。 DIS_H DATA 47H DIS_M DATA 48H DIS_S DATA 49H
標(biāo)簽： 12864 單片機(jī) 液晶時(shí)鐘 顯示程序
上傳時(shí)間： 2013-12-25
上傳用戶：wvbxj
A windows BMP file is a common image format that Java does not handle. While BMP images are used only on windows machines, they are reasonably common. Reading these shows how to read complex structures in Java and how to alter they byte order from the big endian order used by Java to the little endian order used by the windows and the intel processor.
標(biāo)簽： BMP windows common format
上傳時(shí)間： 2013-12-27
上傳用戶：gaojiao1999
Locally weighted polynomial regression LWPR is a popular instance based al gorithm for learning continuous non linear mappings For more than two or three in puts and for more than a few thousand dat apoints the computational expense of pre dictions is daunting We discuss drawbacks with previous approaches to dealing with this problem
標(biāo)簽： polynomial regression weighted instance
上傳時(shí)間： 2013-11-28
上傳用戶：sunjet
Description: C4.5Rule-PANE is a rule learning method which could generate accurate and comprehensible symbolic rules, through regarding a neural network ensemble as a pre-process of a rule inducer. Reference: Z.-H. Zhou and Y. Jiang. Medical diagnosis with C4.5 rule preceded by artificial neural network ensemble. IEEE Transactions on Information Technology in Biomedicine, 2003, vol.7, no.1, pp.37-42. 使用神經(jīng)網(wǎng)絡(luò)集成方法診斷糖尿病,肝炎,乳腺癌癥的案例研究.
標(biāo)簽： comprehensibl Description Rule-PANE accurate
上傳時(shí)間： 2013-11-30
上傳用戶：wcl168881111111
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