This set of files show some of the principles of Monte Carlo simulations, applied in the financila industry. this si the content of the web seminar called "Simulations de Monte Carlo en MATLAB".
ECE345, Visual-to-Audio Electronic Travel Aid
Code for TM320C54x (v2a.asm) download
This project involves the design and implementation of a audio synthesis device that converts moving images into audio signals. The system is built on a TM320C54x DSP with interface to an IMAQ camera module via the serial port on a PC. Brief description: A LabVIEW VI acquires an image from the IMAQ camera module. It quantizes the image into a 5x5, 3-bit image, and sends the data to the TM320C54x DSP via a serial port. The TM320C54x DSP constructs a 64-tap FIR by combining a series of 64-tap head related transfer functions (HRTF) according to the incoming data, and then filters an input audio signal with this FIR filter, in effect creating a correspondence between the filtered signal and the original image.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.
As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface.
Very simple, very small.
tms320lf2407a work with at45db161 "trace".
buffer 8000 word copy from sram to at45.
first page content: num save, to cyclewrite.
function:
read trace to sram, save trace to at45, read status,
and something else
pHash is an implementation of various perceptual hashing algorithms. A perceptual hash is a fingerprint of an audio, video, or image file that is mathematically based on the audio or visual content contained within. Unlike cryptographic hash functions that rely on the avalanche effect of small changes in input leading to drastic changes in the output, perceptual hashes are "close" to one another if the inputs are visually or auditorily similar. As a result, perceptual hashes must also be robust enough to take into account transformations that could have been performed on the input.
USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Supports the four types of USB data transfer control, bulk, interrupt, and isochronous
transfers.
– Host can automatically generate SOF packets.
– 8-bit Wishbone slave bus interface.
– FIFO depth configurable via paramters.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
