GPS 接收程序 DEMO。
HsGpsDll Library 1.1
A GPS Control/Component for C/C++
HsGpsDll is a Windows Dynamic Link Library which provides access to any NMEA-183 compliant GPS RECEIVER via a serial communications port. HsGpsDll is designed for use from Visual C, Visual Basic or other languages, capable of calling DLL functions. HsGpsDll allows a user application to read from a GPS device the current GPS position fix, velocity over ground (speed in kilometers per hour), plus number of of sattelites in view, current altitude (against mean sea level) and UTC date and time
This is GPS in matlab calculatePseudoranges finds relative pseudoranges for all satellites
listed in CHANNELLIST at the specified millisecond of the processed
signal. The pseudoranges contain unknown RECEIVER clock offset. It can be
found by the least squares position search procedure.
Introduction
Matlab is an ideal tool for simulating digital communications systems, thanks to
its easy scripting language and excellent data visualization capabilities. One of the
most frequent simulation tasks in the field of digital communications is bit-error-
rate testing of modems. The bit-error-rate performance of a RECEIVER is a figure of
merit that allows different designs to be compared in a fair manner. Performing
bit-error-rate testing withMatlab is very simple, but does require some prerequisite
knowledge.
We simulate uncoded BER of BPSK modulated
data as a function of SNR
-in an AWGN channel
-in a Rayleigh fading channel
-in an AWGN channel when direct sequence spreading
is used
and compare results to the theoretical ones.
We assume coherent RECEIVER and perfect
synchronization.
A combined space鈥搕ime block coding (STBC) and eigen-space tracking
(EST) scheme in multiple-input-multiple-output systems is
proposed. It is proved that the STBC-EST is capable of shifting
hardware complexity from the RECEIVER to the transmitter without
any bit error rate (BER) performance loss. A computation efficient
EST algorithm is also proposed, which makes the STBC-EST affordable.
Simulation results show that the STBC-EST with a modest
feedback requirement results in a negligible BER performance loss
compared with a dual system configuration.
The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and verification of a digital UART (Universal
Asynchronous RECEIVER & Transmitter).
This file is distributed in the hope that it will be useful, but WITHOUT
WARRANTY OF ANY KIND.
Author(s): Ole Saether
DESCRIPTION:
This example should be used together with ex2a-tx433.asm. One nRF9E5
evaluation board (RECEIVER) should be programmed with the hex-file generated
from assembling this file and the other evaluation board (transmitter)
programmed with the hex-file generated from assembling ex2a-tx433.asm.
All switches on the DIP-swith S206 on the RECEIVER must be set to the "on"
position and all switches on the DIP-swith S205 on the transmitter must be
set to the "on" position.
When one of the switched SW1-SW4 on the transmitter is pressed the
corresponding LED on the RECEIVER is turned on.
The functionality is the same as in ex2c-rx.c.
