本文簡單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
為得到性能優(yōu)良、符合實(shí)際工程的鎖相環(huán)頻率合成器，提出了一種以ADI的仿真工具ADIsimPLL為基礎(chǔ)，運(yùn)用ADS（Advanced Design System 2009）軟件的快速設(shè)計(jì)方法。采用此方法設(shè)計(jì)了頻率輸出為930~960 MHz的頻率合成器。結(jié)果表明該頻率合成器的鎖定時間、相位噪聲以及相位裕度等指標(biāo)均達(dá)到了設(shè)計(jì)目標(biāo)。
