Lab 2 – Synthesizable MATLAB This lab exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab exercise is based on the simple MATLAB FIR filter model shown below:
標簽： MATLAB Synthesizable different exercise
上傳時間： 2015-09-28
上傳用戶：sammi
This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.
標簽： fixed-point conversion introduce AccelDSP
上傳時間： 2015-09-28
上傳用戶：zxc23456789
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture selections that allow full customization of the generated model to the target application requirements.
標簽： AccelWare generators introduce exercise
上傳時間： 2013-12-16
上傳用戶：2467478207
This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore different area/performance tradeoffs.
標簽： capabilities exploration AccelDSP exercise
上傳時間： 2014-12-22
上傳用戶：eclipse
hspice三天入門教程。其中包含多個lab，是新手學習的好資料。
上傳時間： 2014-01-02
上傳用戶：一諾88
幫助文件收集了中國軟件開發實驗室（www.cndev-lab.com）管寧的一些c++方面的文章 希望能幫助初學者在學習的過程中節約不少時間 文章收集及CHM制作：Dludream 推薦C＋＋學習QQ群：5632640 謝謝烈火雨和管寧的支持 有問題可以到我的blog:http://dludream.blogchina.com
標簽： cndev-lab Dludream www CHM
上傳時間： 2015-10-23
上傳用戶：aysyzxzm
The purpose of this lab is to introduce the concept of FSMs with a datapath, and to study the usage of more complex test benches. Also, we enforce a rudimentary design methodology by assuming that the students are part of a bigger project, and have no knowledge of VHDL-implementation of the datapath (made by a hypothetical other group) other than its predefined Entity Interface until they come to the lab. The rest of this document is structured as follows: Section 2 describes some prelimi- nary reading and exercises that should be done before the lab. Section 3 details the design tasks that should be carried out to pass this lab.
標簽： introduce datapath purpose concept
上傳時間： 2014-01-24
上傳用戶：熊少鋒
基于RT-Linux的嵌入式數控系統研究,一些總結
上傳時間： 2015-12-07
上傳用戶：yph853211
RT-Thread是發展中的下一代微內核嵌入式實時操作系統，被設計成一個寬范圍可用的系統，從資源極度緊張的小型系統，到一個帶內存管理單元，網絡功能的基本計算單元。 最新svn版本
上傳時間： 2014-01-21
上傳用戶：hopy
RT-Thread是發展中的下一代微內核嵌入式實時操作系統，被設計成一個寬范圍可用的系統，從資源極度緊張的小型系統，到一個帶內存管理單元，網絡功能的基本計算單元。 最新單內核svn版本
上傳時間： 2014-01-22
上傳用戶：bcjtao
