The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong Reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
Description: S-ISOMAP is a manifold learning algorithm, which is a supervised variant of ISOMAP.
Reference: X. Geng, D.-C. Zhan, and Z.-H. Zhou. Supervised nonlinear dimensionality Reduction for visualization and classification. IEEE Transactions on Systems, Man, and Cybernetics - Part B: Cybernetics, 2005, vol.35, no.6, pp.1098-1107.
The Molgedey and Schuster decorrelation algorithm, having square mixing matrix and no noise . Truncation is used for the time shifted matrix, and it is forced to be symmetric . The delay Tau is estimated .
The number of independent components are calculated using Bayes Information Criterion (BIC), with PCA for dimension Reduction.
Basic Test Concepts
DC Parameters
AC Parameters
Functional Parameters
Device Characterization
Test Program Development
Analog Test Concepts
Test Using DSP Techniques in Testing
Noise Reduction Techniques in Testing
硬件設(shè)計指南(PDF格式)，主要包括：Low Voltage Interfaces；Grounding in Mixed Signal Systems；Digital Isolation Techniques； Power Supply Noise Reduction and Filtering； Dealing with High Speed Logic
We present a particle filter construction for a system that exhibits
time-scale separation. The separation of time-scales allows two simplifications
that we exploit: i) The use of the averaging principle for the
dimensional Reduction of the system needed to solve for each particle
and ii) the factorization of the transition probability which allows the
Rao-Blackwellization of the filtering step. Both simplifications can be
implemented using the coarse projective integration framework. The
resulting particle filter is faster and has smaller variance than the particle
filter based on the original system. The convergence of the new
particle filter to the analytical filter for the original system is proved
and some numerical results are provided.
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency
detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise Reduction when compared to classicalfrequency synthesis.
he algorithm is equivalent to Infomax by Bell and Sejnowski 1995 [1] using a maximum likelihood formulation. No noise is assumed and the number of observations must equal the number of sources. The BFGS method [2] is used for optimization.
The number of independent components are calculated using Bayes Information Criterion [3] (BIC), with PCA for dimension Reduction.
A Matlab toolbox for exact linear time-invariant system identification is presented. The emphasis is on the variety of possible ways to implement the mappings from data to parameters of the data generating system. The considered system representations are input/state/output, difference equation, and left matrix fraction.
KEYWORDS: subspace identification, deterministic subspace identification, balanced model Reduction, approximate system identification, MPUM.
