RFC 1945 Http1.0協(xié)議實現(xiàn)。對協(xié)議進行了完整面向?qū)ο笤O(shè)計，并實現(xiàn)簡單的Http服務(wù)器與客戶端。源碼行數(shù)達4000行。
上傳時間： 2017-06-28
上傳用戶：siguazgb
使用java實現(xiàn)的RFC1945 http1.0協(xié)議。所有面向?qū)ο笤O(shè)計嚴(yán)謹(jǐn)按照RFC 1945協(xié)議中的描述。源代碼逾4000行。提供給Java網(wǎng)絡(luò)編程初學(xué)者學(xué)習(xí)
上傳時間： 2013-12-10
上傳用戶：s363994250
Example script to read CF-compliant structured grid NetCDF data into Matlab using the NetCDF-Java libraryI m using "toolsUI.jar" which is advertised as "a nice fat jar file containing everything in a single jar"
標(biāo)簽： CF-compliant NetCDF-Jav structured Example
上傳時間： 2017-06-30
上傳用戶：gmh1314
IPv6協(xié)議中flow_label的相關(guān)RFC
標(biāo)簽： flow_label IPv6 RFC 協(xié)議
上傳時間： 2017-07-14
上傳用戶：skhlm
中、英文RFC文檔大全打包下載完全版 .
上傳時間： 2013-11-28
上傳用戶：李彥東
A Consumer’s Guide to Using eXpressDSP-Compliant Algorithms
標(biāo)簽： eXpressDSP-Compliant Algorithms Consumer Guide
上傳時間： 2017-08-01
上傳用戶：alan-ee
* TFTP client compatible with RFC-1350 * compile under visiual c++ or borland c++ * author email: yuyushine@163.com ***************************************************/ #define _VC /* if compile under visiual c++ else undefine this*/ #include <stdio.h> #include <winsock.h> #include <conio.h> #ifndef MAKEWORD #define MAKEWORD(l,h) ((WORD)(((BYTE)(l))|(((WORD)(BYTE)(h))<<8))) #endif #define WSA_MAJOR_VERSION 1 #define WSA_MINOR_VERSION 1 #define WSA_VERSION MAKEWORD(WSA_MAJOR_VERSION, WSA_MINOR_VERSION)
標(biāo)簽： compatible borland compile visiual
上傳時間： 2014-01-15
上傳用戶：yuchunhai1990
rfc 3984 文檔 2005年英文pdf版本。
上傳時間： 2013-12-20
上傳用戶：yiwen213
RFC中文文檔大全，為E文不好的網(wǎng)友增加方便！！！
上傳時間： 2013-12-24
上傳用戶：csgcd001
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
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