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S-bus

  • 酒店S-bus智能電氣控制系統方案

    提供酒店智能照明方案

    標簽: S-bus 電氣控制 系統方案

    上傳時間: 2013-10-28

    上傳用戶:liangliang123

  • CANopen is a networking system based on the CAN serial bus. CANopen assumes that the device’s hardw

    CANopen is a networking system based on the CAN serial bus. CANopen assumes that the device’s hardware has a CAN transceiver and CAN controller as specified in ISO 11898. CANopen profile family specifies standardized communication mechanisms and device functionality. The profile family is available and maintained by CAN in Automation (CiA), the international users’ and manufacturers’ group and may be implemented license-free.

    標簽: CANopen networking the assumes

    上傳時間: 2013-12-26

    上傳用戶:q123321

  • *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 2

    *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.

    標簽: Microchip Routines Sample WRITE

    上傳時間: 2013-12-27

    上傳用戶:ljmwh2000

  • 8-bit I2C-bus and SMBus IO port with reset

    The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.

    標簽: C-bus SMBus reset port

    上傳時間: 2014-01-18

    上傳用戶:bs2005

  • The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the d

    The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video.

    標簽: bottleneck developed the concept

    上傳時間: 2014-12-03

    上傳用戶:ikemada

  • The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the d

    The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video. Hardware reference

    標簽: bottleneck developed the concept

    上傳時間: 2016-03-18

    上傳用戶:極客

  • The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the d

    The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video. User Manual

    標簽: bottleneck developed the concept

    上傳時間: 2014-01-15

    上傳用戶:努力努力再努力

  • Back in 2002, the 6502 disappeared out of all catalogues. Wanted to know, if it s possible to buil

    Back in 2002, the 6502 disappeared out of all catalogues. Wanted to know, if it s possible to build a binary compatible CPU with the things I had in the drawer: 74LS parts, 27C512 EPROMs and a fast static RAM from an old 80386 motherboard. Now here the results. Note, that the Bus timing is different from the 6502.

    標簽: disappeared catalogues possible Wanted

    上傳時間: 2016-04-09

    上傳用戶:hn891122

  • The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co

    The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.

    標簽: bus bidirectional primarily designed

    上傳時間: 2013-12-11

    上傳用戶:jeffery

  • This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to

    This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-bus Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.

    標簽: This microprocessor describes S3C2410A

    上傳時間: 2013-11-30

    上傳用戶:GavinNeko

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