所學(xué)的指令LD、LDI、OUT AND、ANI OR、 ORI LDP、 LDF、ANDP、ANDF、 ORP、 ORF ORB、 ANB MPS、 MRD、 MPP MC、 MCRSET RSTNOP END 自鎖電路觸點(diǎn)的動(dòng)作發(fā)光二極管的工作原理。八段碼顯示是利用發(fā)光二極管的不同段碼組合來(lái)實(shí)現(xiàn)的，它可以實(shí)現(xiàn)0到F的顯示。搶答器的顯示就是利用八段碼顯示的特性，來(lái)完成幾個(gè)不同組別的顯示。用PLC實(shí)現(xiàn)八段碼顯示0～9組的3組以上搶答器的程序編寫(xiě)，并完成以下要求：1）設(shè)計(jì)由PLC實(shí)現(xiàn)的八段碼顯示0～9組的3組以上搶答器的程序編寫(xiě)，并完成以下要求： ①列出PLC的輸入輸出地址分配表 ②畫(huà)出PLC的輸入輸出接線圖（即I/O接線圖） ③設(shè)計(jì)PLC的梯形圖 ④根據(jù)梯形圖列寫(xiě)指令表 2）按PLC控制I/O口（輸入/輸出）接線圖在模擬實(shí)驗(yàn)設(shè)備上正確接線。
上傳時(shí)間： 2013-11-22
上傳用戶：lmeeworm
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽： synchronous Emulating serial
上傳時(shí)間： 2014-01-31
上傳用戶：z1191176801
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
標(biāo)簽： routines driver P90 301
上傳時(shí)間： 2013-11-23
上傳用戶：weixiao99
This application note demonstrates how to write an Inter Integrated Circuit bus driver (I2C) for the XA-S3 16-bitMicrocontroller from Philips Semiconductors.Not only the driver software is given. This note also contains a set of (example) interface routines and a smalldemo application program. All together it offers the user a quick start in writing a complete I2C system applicationwith the PXAS3x.The driver routines support interrupt driven single master transfers. Furthermore, the routines are suitable foruse in conjunction with real time operating systems.
標(biāo)簽： software driver XA-S I2C
上傳時(shí)間： 2013-11-02
上傳用戶：zw380105939
提出了一個(gè)由AT89C52單片機(jī)控制步進(jìn)電機(jī)的實(shí)例。可以通過(guò)鍵盤(pán)輸入相關(guān)數(shù)據(jù), 并根據(jù)需要, 實(shí)時(shí)對(duì)步進(jìn)電機(jī)工作方式進(jìn)行設(shè)置, 具有實(shí)時(shí)性和交互性的特點(diǎn)。該系統(tǒng)可應(yīng)用于步進(jìn)電機(jī)控制的大多數(shù)場(chǎng)合。實(shí)踐表明, 系統(tǒng)性能優(yōu)于傳統(tǒng)的步進(jìn)電機(jī)控制器。關(guān)鍵詞: 單片機(jī); 步進(jìn)電動(dòng)機(jī); 直流固態(tài)繼電器; 實(shí)時(shí)控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
標(biāo)簽： Control System ingMot Stepp
上傳時(shí)間： 2013-11-19
上傳用戶：leesuper
MCSÉ-51 Programmer's Guide and Instruction Set The information presented in this chapter is collected from the MCSÉ-51 Architectural Overview and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
標(biāo)簽： Program Eacute MCS 51
上傳時(shí)間： 2013-11-13
上傳用戶：hj_18
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上傳時(shí)間： 2013-11-10
上傳用戶：1427796291
什么是JTAG 到底什么是JTAG呢？ JTAG(Joint Test Action Group)聯(lián)合測(cè)試行動(dòng)小組)是一種國(guó)際標(biāo)準(zhǔn)測(cè)試協(xié)議（IEEE 1149.1兼容），主要用于芯片內(nèi)部測(cè)試。現(xiàn)在多數(shù)的高級(jí)器件都支持JTAG協(xié)議，如DSP、FPGA器件等。標(biāo)準(zhǔn)的JTAG接口是4線：TMS、 TCK、TDI、TDO，分別為模式選擇、時(shí)鐘、數(shù)據(jù)輸入和數(shù)據(jù)輸出線。 JTAG最初是用來(lái)對(duì)芯片進(jìn)行測(cè)試的，基本原理是在器件內(nèi)部定義一個(gè)TAP（Test Access Port�測(cè)試訪問(wèn)口）通過(guò)專用的JTAG測(cè)試工具對(duì)進(jìn)行內(nèi)部節(jié)點(diǎn)進(jìn)行測(cè)試。JTAG測(cè)試允許多個(gè)器件通過(guò)JTAG接口串聯(lián)在一起，形成一個(gè)JTAG鏈，能實(shí)現(xiàn)對(duì)各個(gè)器件分別測(cè)試。現(xiàn)在，JTAG接口還常用于實(shí)現(xiàn)ISP（In-System rogrammable�在線編程），對(duì)FLASH等器件進(jìn)行編程。 JTAG編程方式是在線編程，傳統(tǒng)生產(chǎn)流程中先對(duì)芯片進(jìn)行預(yù)編程現(xiàn)再裝到板上因此而改變，簡(jiǎn)化的流程為先固定器件到電路板上，再用JTAG編程，從而大大加快工程進(jìn)度。JTAG接口可對(duì)PSD芯片內(nèi)部的所有部件進(jìn)行編程 JTAG的一些說(shuō)明 通常所說(shuō)的JTAG大致分兩類，一類用于測(cè)試芯片的電氣特性，檢測(cè)芯片是否有問(wèn)題；一類用于Debug；一般支持JTAG的CPU內(nèi)都包含了這兩個(gè)模塊。 一個(gè)含有JTAG Debug接口模塊的CPU，只要時(shí)鐘正常，就可以通過(guò)JTAG接口訪問(wèn)CPU的內(nèi)部寄存器和掛在CPU總線上的設(shè)備，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）內(nèi)置模塊的寄存器，象UART，Timers，GPIO等等的寄存器。 上面說(shuō)的只是JTAG接口所具備的能力，要使用這些功能，還需要軟件的配合，具體實(shí)現(xiàn)的功能則由具體的軟件決定。 例如下載程序到RAM功能。了解SOC的都知道，要使用外接的RAM，需要參照SOC DataSheet的寄存器說(shuō)明，設(shè)置RAM的基地址，總線寬度，訪問(wèn)速度等等。有的SOC則還需要Remap，才能正常工作。運(yùn)行Firmware時(shí)，這些設(shè)置由Firmware的初始化程序完成。但如果使用JTAG接口，相關(guān)的寄存器可能還處在上電值，甚至?xí)r錯(cuò)誤值，RAM不能正常工作，所以下載必然要失敗。要正常使用，先要想辦法設(shè)置RAM。在ADW中，可以在Console窗口通過(guò)Let 命令設(shè)置，在AXD中可以在Console窗口通過(guò)Set命令設(shè)置。
上傳時(shí)間： 2013-10-23
上傳用戶：aeiouetla
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
介紹了AES中,SubBytes算法在FPGA的具體實(shí)現(xiàn).構(gòu)造SubBytes的S-Box轉(zhuǎn)換表可以直接查找ROM表來(lái)實(shí)現(xiàn).通過(guò)分析SubBytes算法得到一種可行性硬件邏輯電路,從而實(shí)現(xiàn)SubBytes變換的功能.
標(biāo)簽： SubBytes FPGA AES 算法
上傳時(shí)間： 2013-11-30
上傳用戶：hzy5825468
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