This application note shows how to achieve low-cost, efficient serial configuration for SPartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing SPartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a SPartan design in the field by sending thebitstream over a network.
標簽：
SPartan
XAPP
FPGA
098
上傳時間：
2014-08-16
上傳用戶：adada
