Wherever possible the overall technique used for this series will be "definition by example" withgeneric formulae included for use in other applications. To make stability analysis easy we will usemore than one tool from our toolbox with data sheet information, tricks, rules-of-thumb, SPICESimulation, and real-world testing all accelerating our design of STABLE operational amplifier (op amp)circuits. These tools are specifically targeted at voltage feedback op amps with unity-gain bandwidths<20 MHz, although many of the techniques are applicable to any voltage feedback op amp. 20 MHz ischosen because as we increase to higher bandwidth circuits there are other major factors in closing theloop: such as parasitic capacitances on PCBs, parasitic inductances in capacitors, parasitic inductancesand capacitances in resistors, etc. Most of the rules-of-thumb and techniques were developed not justfrom theory but from the actual building of real-world circuits with op amps <20 MHz.
標簽： 運算放大器
上傳時間： 2021-11-01
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with STABLE Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
針對嵌入式產品程序更新問題,提出了一種基于IAP技術的STM32單片機在線固件升級方案,設計了STM32單片機最小系統硬件電路和USB轉串口通信電路,并給出了Bootloader程序、APP程序、PC上機程序的實現流程.實驗結果表明,該方案具有簡單實用、穩定性高、維護成本低和設備使用效率高的特點,適用于嵌入式產品升級.For the problem of updating embedded products program,an online firmware upgrade scheme of STM32 single chip microcomputer based on IAP technology is proposed.This scheme not only elaborates the principle of IAP technology in detail but also provides the design of the minimum system hardware circuit of STM32 MCU,the design of USB for serial communication circuit,and the implementation flow of Bootloader program,APP program and PC program.The experiment results show that the scheme is simple,practical and highly STABLE.In addition,it can be used to actual embedded product upgrading,significantly reducing maintenance costs and improving the efficiency of equipment.
上傳時間： 2022-03-25
上傳用戶：
對某四輪獨立驅動電動汽車輪轂電機進行研究,設計一種永磁無刷直流電機控制器.以STM32F103RBT6芯片為基礎,對電機驅動電路、采樣電路和保護電路分別進行硬件設計與分析;同時,采用模塊化軟件設計方案,對該控制器的軟件系統進行升級.實驗驗證表明:所設計的電機控制器能使電機響應迅速、轉速穩定、無超調,且電動車動力輸出性能良好.A permanent magnet brushless direct current motor controller was designed by studying the hub motor of a four-wheel independent drive electric vehicle.Based on STM32 F103RBT6 chip,the hardware design and analysis of motor drive circuit,sampling circuit and protection circuit were carried out respectively.At the same time,modular software design scheme was adopted to upgrade the software system of the controller.Experimental results show that the designed motor controller can ensure the motor fast response,STABLE speed,no overshoot,and good power output performances.
上傳時間： 2022-03-26
上傳用戶：qingfengchizhu
為設計高效率、低損耗的PFC電路,本文基于UCC28019進行電路設計。以UCC28019輸出的PWM波形來控制Boost升壓斬波為核心電路,使電路中的電容交替地充放電、電感交替的儲存和釋放能量,最后實現在輸入AC20V~24V電壓情況下穩定輸出DC38V。測試結果表明,系統實現效率為95%左右,電壓調整率小于1%,電源功率因數0.99。交流輸入電壓為19.0-25.8 V時,輸出直流電壓穩定性較好,電感無明顯嘯叫且紋波小,具有一定的帶負載能力和實用性。In order to design the PFC circuit with high efficiency and low loss,this paper designs the circuit based on UCC28019.The PWM waveform output by UCC28019 is used to control boost chopper as the core circuit,which alternately charges and discharges capacitors,stores and releases energy by inductors,and finally achieves STABLE output of DC38 V under the input voltage of AC20 V~24 V.The test results show that the system achieves about 95% efficiency,the voltage adjustment rate is less than 1%,the power factor is 0.99,and the AC input voltage is 19.0-25.8 V.The output DC voltage stability is good,the inductance has no obvious whistle and the ripple is small,so it has certain load capacity and practicability.
上傳時間： 2022-04-03
上傳用戶：
基于PSIM仿真軟件，分析了Boost電路拓撲結構，設定了參數要求進行電路仿真設計，通過電路仿真軟件PSIM對Boost電路工作在CCM模式下，合理設置占空比參數。實驗結果表明理論分析與仿真的一致性和參數設計的正確性，輸出電壓和電流參數穩定，Boost電路輸出效率高。This design is based on PSIM simulation software,analyzes the topology of Boost circuit,sets the parameter re- quirements for circuit simulation design,and reasonably sets the duty cycle parameters for Boost circuit working in CCM mode through PSIM simulation software.The experimental results show that the theoretical analysis and simulation are consis- tent and the parameter design is correct,the output voltage and current parameters are STABLE.
上傳時間： 2022-05-04
上傳用戶：
