本文論述了狀態機的verilog編碼風格,以及不同編碼風格的優缺點，STEVE Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. STEVE's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標簽：
Synthesis
Machine
Coding
Styles
上傳時間：
2013-10-12
上傳用戶：sardinescn
