The Circuit Designer’s Companion Second edition Tim Williams
標簽： Designers Companion Circuit PCB
上傳時間： 2013-11-04
上傳用戶：fredguo
Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the Second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
標簽： EMI 開關(guān)電源 英文
上傳時間： 2013-11-10
上傳用戶：1595690
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The Second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2013-10-15
上傳用戶：busterman
In this paper, two types of MMIC voltage controlled oscillators have been successfully demonstrated. The first chip with single tuning diode shows the excellent tuning linearity. The Second chip with two tuning diodes can improve the tuning bandwidth.
上傳時間： 2013-10-17
上傳用戶：xjz632
在深入了解Flash存儲器的基礎(chǔ)上，采用單片機自動檢測存儲器無效塊。主要通過讀取每一塊的第1、第2頁內(nèi)容，判斷該塊的好壞，并給出具體的實現(xiàn)過程，以及部分關(guān)鍵的電路原理圖和C語言程序代碼。該設(shè)計最終實現(xiàn)單片機自動檢測Flash壞塊的功能，并通過讀取ID號檢測Flash的性能，同時該設(shè)計能夠存儲和讀取1GB數(shù)據(jù)。 Abstract: On the basis of in-depth understanding the Flash chips，this paper designs a new program which using the SCM to detect the invalid block.Mainly through reading the data of the first and Second page to detect the invalid block.Specific implementation procedure was given,and the key circuit schematic diagram and C language program code was introduced.This design achieved the function of using the MCU checks the invalid block finally，and increased the function by reading the ID number of Flash to get the performance of the memory.And the design also can write and read1GB data
上傳時間： 2013-10-25
上傳用戶：taozhihua1314
What is New in C51 Version 8.18[Device Support]Added debug support for the NXP P89LPC9408 in the LPC900 EPM Emulator/Programmer.[New Supported Device]Nuvoton W681308 device.[New Supported Device]NXP P89LPC9201, P89LPC9211, P89LPC922A1, P89LPC9241, P89LPC9251, P89LPC9301, P89LPC931A1, P89LPC9331, P89LPC9341, and P89LPC9351 devices.[New Supported Device]SiLabs C8051F500, C8051F501, C8051F504, C8051F505, C8051F506, C8051F507, C8051F508, C8051F509, C8051F510, and C8051F511 devices.[ULINK2 Support]Corrected potential deadlock on ST uPSD targets.[Device Simulation]Corrected simulation of Infineon XC800 MDU.[Device Simulation]Corrected behaviour of EXFn and TOGn on SiLabs C8051F12x/F13x devices.[Device Simulation]Added simulation for Atmel AT89C51RE2, including simulation of Second UART.[Cx51 Compiler]Corrected failed initialization on far addresses when the object is located with _at_. 本資料僅供學習評估之用,請勿用于商業(yè)用途!請在學習評估24小時內(nèi)刪除.
上傳時間： 2013-11-01
上傳用戶：panpanpan
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a Second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標簽： synchronous Emulating serial
上傳時間： 2014-01-31
上傳用戶：z1191176801
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the Second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
上傳時間： 2013-10-27
上傳用戶：zhangyigenius
The Infineon TriCore provides an Interrupt System with a high safety standard. Thisdocument contains some instructions on how to initiate an Interrupt from an externaldevice. First it will show you how to trigger an Interrupt Service Request by an impulseon Port 0 or Port 1. Then in the Second part of the document you can find hints how todebounce impulses to enable the use of a simple switch as input device.Authors: Thomas Bliem, CQ Nguyen / Infineon SMI MD Apps
上傳時間： 2013-11-05
上傳用戶：uuuuuuu
微處理器及微型計算機的發(fā)展概況 第一代微處理器是以Intel公司1971年推出的4004，4040為代表的四位微處理機。 第二代微處理機（1973年~1977年），典型代表有：Intel 公司的8080、8085；Motorola公司的M6800以及Zlog公司的Z80。 第三代微處理機 第三代微機是以16位機為代表，基本上是在第二代微機的基礎(chǔ)上發(fā)展起來的。其中Intel公司的8088。8086是在8085的基礎(chǔ)發(fā)展起來的；M68000是Motorola公司在M6800 的基礎(chǔ)發(fā)展起來的； 第四代微處理機 以Intel公司1984年10月推出的80386CPU和1989年4月推出的80486CPU為代表， 第五代微處理機的發(fā)展更加迅猛，1993年3月被命名為PENTIUM的微處理機面世，98年P(guān)ENTIUM 2又被推向市場。 INTEL CPU 發(fā)展歷史Intel第一塊CPU 4004,4位主理器,主頻108kHz,運算速度0.06MIPs(Million Instructions Per Second, 每秒百萬條指令),集成晶體管2,300個,10微米制造工藝,最大尋址內(nèi)存640 bytes,生產(chǎn)曰期1971年11月. 8085,8位主理器,主頻5M,運算速度0.37MIPs,集成晶體管6,500個,3微米制造工藝,最大尋址內(nèi)存64KB,生產(chǎn)曰期1976年 8086,16位主理器,主頻4.77/8/10MHZ,運算速度0.75MIPs,集成晶體管29,000個,3微米制造工藝,最大尋址內(nèi)存1MB,生產(chǎn)曰期1978年6月. 80486DX,DX2,DX4,32位主理器,主頻25/33/50/66/75/100MHZ,總線頻率33/50/66MHZ,運算速度20~60MIPs,集成晶體管1.2M個,1微米制造工藝,168針PGA,最大尋址內(nèi)存4GB,緩存8/16/32/64KB,生產(chǎn)曰期1989年4月 Celeron一代, 主頻266/300MHZ(266/300MHz w/o L2 cache, Covington芯心 (Klamath based),300A/333/366/400/433/466/500/533MHz w/128kB L2 cache, Mendocino核心 (Deschutes-based), 總線頻率66MHz,0.25微米制造工藝,生產(chǎn)曰期1998年4月) Pentium 4 (478針),至今分為三種核心:Willamette核心(主頻1.5G起,FSB400MHZ,0.18微米制造工藝),Northwood核心(主頻1.6G~3.0G,FSB533MHZ,0.13微米制造工藝, 二級緩存512K),Prescott核心(主頻2.8G起,FSB800MHZ,0.09微米制造工藝,1M二級緩存,13條全新指令集SSE3),生產(chǎn)曰期2001年7月. 更大的緩存、更高的頻率、 超級流水線、分支預(yù)測、亂序執(zhí)行超線程技術(shù) 微型計算機組成結(jié)構(gòu)單片機簡介單片機即單片機微型計算機，是將計算機主機(CPU、 內(nèi)存和I/O接口)集成在一小塊硅片上的微型機。 三、計算機編程語言的發(fā)展概況 機器語言 機器語言就是0，1碼語言，是計算機唯一能理解并直接執(zhí)行的語言。匯編語言 用一些助記符號代替用0，1碼描述的某種機器的指令系統(tǒng)，匯編語言就是在此基礎(chǔ)上完善起來的。高級語言 BASIC，PASCAL，C語言等等。用高級語言編寫的程序稱源程序，它們必須通過編譯或解釋，連接等步驟才能被計算機處理。 面向?qū)ο笳Z言 C++，Java等編程語言是面向?qū)ο蟮恼Z言。 1.3 微型計算機中信息的表示及運算基礎(chǔ)（一） 十進制ND有十個數(shù)碼：0～9，逢十進一。 例 1234.5=1×103 +2×102 +3×101 +4×100 +5×10-1加權(quán)展開式以10稱為基數(shù)，各位系數(shù)為0～9，10i為權(quán)。 一般表達式：ND= dn-1×10n-1+dn-2×10n-2 +…+d0×100 +d-1×10-1+… （二） 二進制NB兩個數(shù)碼：0、1, 逢二進一。 例 1101.101=1×23+1×22+0×21+1×20+1×2-1+1×2-3 加權(quán)展開式以2為基數(shù)，各位系數(shù)為0、1， 2i為權(quán)。 一般表達式： NB = bn-1×2n-1 + bn-2×2n-2 +…+b0×20 +b-1×2-1+… （三）十六進制NH十六個數(shù)碼0～9、A～F，逢十六進一。 例：DFC.8=13×162 +15×161 +12×160 +8×16-1 展開式以十六為基數(shù)，各位系數(shù)為0～9，A～F，16i為權(quán)。 一般表達式： NH= hn-1×16n-1+ hn-2×16n-2+…+ h0×160+ h-1×16-1+… 二、不同進位計數(shù)制之間的轉(zhuǎn)換 （二）二進制與十六進制數(shù)之間的轉(zhuǎn)換 24=16 ，四位二進制數(shù)對應(yīng)一位十六進制數(shù)。舉例：（三）十進制數(shù)轉(zhuǎn)換成二、十六進制數(shù)整數(shù)、小數(shù)分別轉(zhuǎn)換 1.整數(shù)轉(zhuǎn)換法“除基取余”：十進制整數(shù)不斷除以轉(zhuǎn)換進制基數(shù)，直至商為0。每除一次取一個余數(shù)，從低位排向高位。舉例： 2. 小數(shù)轉(zhuǎn)換法“乘基取整”：用轉(zhuǎn)換進制的基數(shù)乘以小數(shù)部分，直至小數(shù)為0或達到轉(zhuǎn)換精度要求的位數(shù)。每乘一次取一次整數(shù)，從最高位排到最低位。舉例： 三、帶符號數(shù)的表示方法 機器數(shù)：機器中數(shù)的表示形式。真值： 機器數(shù)所代表的實際數(shù)值。舉例:一個8位機器數(shù)與它的真值對應(yīng)關(guān)系如下： 真值： X1=+84=+1010100B X2=-84= -1010100B 機器數(shù)：[X1]機= 01010100 [X2]機= 11010100(二)原碼、反碼、補碼最高位為符號位，0表示 “+”，1表示“－”。 數(shù)值位與真值數(shù)值位相同。 例 8位原碼機器數(shù)： 真值： x1 = +1010100B x2 =－ 1010100B 機器數(shù)： [x1]原 = 01010100 [x2]原 = 11010100原碼表示簡單直觀,但0的表示不唯一，加減運算復(fù)雜。 正數(shù)的反碼與原碼表示相同。 負數(shù)反碼符號位為 1，數(shù)值位為原碼數(shù)值各位取反。 例 8位反碼機器數(shù)： x= +4： [x]原= 00000100 [x]反= 00000100 x= -4： [x]原= 10000100 [x]反= 111110113、補碼（Two’s Complement）正數(shù)的補碼表示與原碼相同。 負數(shù)補碼等于2n－abs（x）8位機器數(shù)表示的真值四、 二進制編碼例：求十進制數(shù)876的BCD碼 876= 1000 0111 0110 BCD 876= 36CH = 1101101100B 2、字符編碼 美國標準信息交換碼ASCII碼，用于計算 機與計算機、計算機與外設(shè)之間傳遞信息。 3、漢字編碼 “國家標準信息交換用漢字編碼”（GB2312-80標準），簡稱國標碼。 用兩個七位二進制數(shù)編碼表示一個漢字 例如“巧”字的代碼是39H、41H漢字內(nèi)碼例如“巧”字的代碼是0B9H、0C1H1·4 運算基礎(chǔ) 一、二進制數(shù)的運算加法規(guī)則：“逢2進1” 減法規(guī)則：“借1當2” 乘法規(guī)則：“逢0出0，全1出1”二、二—十進制數(shù)的加、減運算 BCD數(shù)的運算規(guī)則 循十進制數(shù)的運算規(guī)則“逢10進1”。但計算機在進行這種運算時會出現(xiàn)潛在的錯誤。為了解決BCD數(shù)的運算問題，采取調(diào)整運算結(jié)果的措施：即“加六修正”和“減六修正”例：10001000(BCD)+01101001(BCD) =000101010111(BCD) 1 0 0 0 1 0 0 0 ＋ 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 1 ＋ 0 1 1 0 0 1 1 0 ……調(diào)整 1 0 1 0 1 0 1 1 1 進位 例： 10001000(BCD)－ 01101001(BCD)= 00011001(BCD) 1 0 0 0 1 0 0 0 － 0 1 1 0 1 0 0 1 0 0 0 1 1 1 1 1 － 0 1 1 0 ……調(diào)整 0 0 0 1 1 0 0 1 三、 帶符號二進制數(shù)的運算 1.5 幾個重要的數(shù)字邏輯電路編碼器譯碼器計數(shù)器微機自動工作的條件程序指令順序存放自動跟蹤指令執(zhí)行1.6 微機基本結(jié)構(gòu)微機結(jié)構(gòu)各部分組成連接方式1、以CPU為中心的雙總線結(jié)構(gòu)；2、以內(nèi)存為中心的雙總線結(jié)構(gòu)；3、單總線結(jié)構(gòu)CPU結(jié)構(gòu)管腳特點 1、多功能；2、分時復(fù)用內(nèi)部結(jié)構(gòu) 1、控制; 2、運算; 3、寄存器; 4、地址程序計數(shù)器堆棧定義 1、定義；2、管理；3、堆棧形式
上傳時間： 2013-10-17
上傳用戶：erkuizhang
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