Delphi and C++ Builder component for direct access to IO ports on Windows 95, Windows 98 and Windows NT/2000. Provides properties for reading and writing bytes, words and doublewords from/to IO ports. New fast block data transfer methods enable to read and write megabytes of data per Second.
Input
The first line of the input contains a single integer T (1 <= T <= 20), the number of test cases. Then T cases follow. The first line of each case contains N, and the Second line contains N integers giving the time for each people to cross the river. Each case is preceded by a blank line. There won t be more than 1000 people and nobody takes more than 100 Seconds to cross.
Output
For each test case, print a line containing the total number of Seconds required for all the N people to cross the river.
Sample Input
1
4
1 2 5 10
Sample Output
17
Input
The input contains blocks of 2 lines. The first line contains the number of sticks parts after cutting, there are at most 64 sticks. The Second line contains the lengths of those parts separated by the space. The last line of the file contains zero.
Output
The output should contains the smallest possible length of original sticks, one per line.
Sample Input
9
5 2 1 5 2 1 5 2 1
4
1 2 3 4
0
Sample Output
6
5
Input
The input consists of two lines. The first line contains two integers n and k which are the lengths of the array and the sliding window. There are n integers in the Second line.
Output
There are two lines in the output. The first line gives the minimum values in the window at each position, from left to right, respectively. The Second line gives the maximum values.
Sample Input
8 3
1 3 -1 -3 5 3 6 7
Sample Output
-1 -3 -3 -3 3 3
3 3 5 5 6 7
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer
desktop motherboard. The material covered can be broken into three main categories: Board design
guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an
explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per
Second on an actual motherboard. Section 7 contains a design checklist that lists each design
recommendation described in this document. High speed USB operation is described in the USB 2.0
Specification (http://www.usb.org/developers/docs.html).
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer
desktop motherboard. The material covered can be broken into three main categories: Board design
guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an
explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per
Second on an actual motherboard. Section 7 contains a design checklist that lists each design
recommendation described in this document. High speed USB operation is described in the USB 2.0
Specification (http://www.usb.org/developers/docs.html).
There are many different (and often confusing) terms associated
with clock-based devices. This application note attempts
to clarify these terms, and hence serves as a comprehensive
reference on clock terminology. This application note can be
divided into two sections. The first section describes and distinguishes
between various clock sources available today.
The Second section defines and distinguishes between various
parameters used to describe clocks. This section also provides methods of measuring some of these parameters.
Universal Serial Bus (USB) is a communications architecture that gives a personal
computer (PC) the ability to interconnect a variety of devices using a simple four-
wire cable. The USB is actually a two-wire serial communication link that runs at
either 1.5 or 12 megabits per Second (mbs). USB protocols can configure devices
at startup or when they are plugged in at run time. These devices are broken into
various device classes. Each device class defines the common behavior and
protocols for devices that serve similar functions. Some examples of USB device
classes are shown in the following table
DAGON Approach
Object of this exercise:
Given a subject graph and a set of pattern graph in canonical representation (2-input
NAND and INV), implement the Second step of DAGON approach. (Both the subject
graph and the pattern graphs are trees.)
