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用于蛋白質數據生成分類數據的轉換。做PSS（Protein Secondary Structure prediction)的可以參考一下。
標簽： prediction Secondary Structure Protein
上傳時間： 2013-12-22
上傳用戶：SimonQQ
易飛ERP二次開發接口制作完成 Yi-fei ERP finished Secondary development interface
標簽： development ERP Secondary interface
上傳時間： 2013-12-08
上傳用戶：aappkkee
dm6437的NAND Secondary Boot，很好用，有原代碼
上傳時間： 2013-12-23
上傳用戶：541657925
二次雷達(Secondary Surveillance Radar)是民航空中管制(Air Traffic Control)和軍事敵我識別(Identification Friend or Foe)系統中的關鍵部分,由于這兩個應用領域都要求很高的可靠性和穩定性,因此,二次雷達一直是國內外雷達信號處理領域的研究熱點.傳統的機載二次雷達應答器普遍采用中小規模集成電路和分立元件設計,其穩定性和可靠性差,實時處理能力也很有限,無法完成高密度、大容量的應答.針對這些缺陷,本論文提出一種全新的應答數字信號處理器硬件結構,即FPGA+DSP的混合結構.這種硬件體系結構的特點是可靠性高,集成度高,通用性強,適于模塊化設計,處理速度快,能實時處理多個應答信號,以及進行置信度分析和生成報表.此項目中,本文作者主要負責FPGA部分硬件設計.FPGA主要完成雙通道數據采集、產生視頻信號和旁瓣抑制信號、計算當前飛機相對本地接收天線的方位和距離、與DSP實時交換數據、上傳報表等功能.論文詳細分析了接收機信號處理算法在FPGA中的硬件實現方案,在提高系統可靠性、堅固性以及FPGA資源的合理利用方面做了深入的探討.同時給出不同層次關鍵模塊的HDL實現及其時序仿真結果.
上傳時間： 2013-04-24
上傳用戶：西伯利亞狼
One of the most critical components in a step-up design like Figure 1 is the transformer. Transformers have parasitic components that can cause them to deviate from their ideal characteristics, and the parasitic capacitance associated with the Secondary can cause large resonating current spikes on the leading edge of the switch current waveform.
上傳時間： 2013-11-22
上傳用戶：15070202241
While simplicity and high effi ciency (for cool running) areno longer optional features in isolated power supplies, itis traditionally diffi cult to achieve both. Achieving higheffi ciency often requires the use of advanced topologiesand home-brewed Secondary synchronous rectifi cationschemes once reserved only for higher power applications.This only adds to the parts count and to the designcomplexity associated with the reference and optocouplercircuits typically used to maintain isolation. Fortunately, abreakthrough IC makes it possible to achieve both high efficiency and simplicity in a synchronous fl yback topology.The LT®3825 simplifi es and improves the performance oflow voltage, high current fl yback supplies by providingprecise synchronous rectifi er timing and eliminating theneed for optocoupler feedback while maintaining excellentregulation and superior loop response.
上傳時間： 2013-10-16
上傳用戶：wayne595
Many system designers need an easy way to producea negative 3.3V power supply. In systems that alreadyhave a transformer, one option is to swap out the existingtransformer with one that has an additional Secondarywinding. The problem with this solution is that manysystems now use transformers that are standard, offthe-shelf components, and most designers want toavoid replacing a standard, qualifi ed transformer with acustom version. An easier alternative is to produce thelow negative voltage rail by stepping down an existingnegative rail. For example, if the system already employsan off-the-shelf transformer with two Secondary windingsto produce ±12V, and a –3.3V rail is needed, a negativebuck converter can produce the –3.3V output from the–12V rail.
上傳時間： 2013-10-09
上傳用戶：Jerry_Chow
為了有效地提升鉛酸蓄電池的使用壽命，同時實現對充電過程的監控，設計出一種用單片機控制的36 V鉛酸蓄電池充電電源。本電路采用反激式拓撲，連續電流工作模式，電源管理IC設計在電源的副邊，由ELAN公司的EM78P258N單片機模擬，是用可編程器件模擬電源管理IC，實現智能電源低成本化的一次成功嘗試，通過對單片機的軟件設計實現了充電電源的狀態顯示、充電時間控制、報警、過溫保護、過壓保護、過流保護等功能。本充電器真正的實現了鉛酸蓄電池的三段式充電過程，其最高輸出功率可達90 W，效率約85%，成本不到20元，具有很高的市場競爭力。 Abstract: In order to extend the life of lead-acid battery efficiently and supervise the charging process meanwhile， a 36V lead-acid battery charge powe supply controlled by microcontroller is designed. The charger is flyback switching power supply and works in CCM mode. A EM78P258N microcontroller made by ELAN microelectronics corporation is used as power management IC which is designed at the Secondary circuit. The project is a successful attempt to low-cost intelligent power used microcontroller simulating power management IC. The charger also has the functions of the status reveal， charge time control， alarming， thermal protect， current limit and overvoltage protect by the software design. The circuit actually implements the three-step charge process， whose power is up to 90W and whose efficiency can get 85%. The net cost of this charger is less than 20 RMB， so that the charger is of powerful market competitiveness.
上傳時間： 2013-11-16
上傳用戶：cepsypeng
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a Secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上傳時間： 2013-10-08
上傳用戶：18711024007
The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
標簽： Demonstration 3200 USB for
上傳時間： 2014-02-27
上傳用戶：zhangzhenyu
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