The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be Selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
The PCA9546A is a quad bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be Selected, determined by thecontents of the programmable control register.
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be Selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be Selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deSelected as does the internalPower-on reset function.
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be Selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be Selected, depending on the content of the programmable control register. Once one or several channels have been Selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
MCSÉ-51 Programmer's Guide and Instruction Set
The information presented in this chapter is collected from the MCSÉ-51 Architectural Overview and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been Selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message Selected at another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.
This book evolved over the past ten years from a set of lecture notes developed while teaching
the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching
this course evolved tremendously over these years in a number of directions, partly to address
our students' background (undeveloped formal skills outside of programming), and partly to
reect the maturing of the eld in general, as we have come to see it. The notes increasingly
crystallized into a narrative, and we progressively structured the course to emphasize the
?story line? implicit in the progression of the material. As a result, the topics were carefully
Selected and clustered. No attempt was made to be encyclopedic, and this freed us to include
topics traditionally de-emphasized or omitted from most Algorithms books.
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be Selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message Selected at another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.
