該程序設(shè)計(jì)了一個(gè)產(chǎn)生PCM碼流時(shí)序信號(hào)的模塊，他包括輸入端CLK，SET及輸出端Q1,Q2,Q3
標(biāo)簽： PCM 程序設(shè)計(jì) 碼流 時(shí)序
上傳時(shí)間： 2014-01-09
上傳用戶(hù)：wweqas
Quality, object.oriented architecture is the product of careful study, decision making, and experimentation. At a minimum, the object.oriented architecture process includes farming of requirements, architecture mining, and hands.on experience. Ideally, object.oriented architecture comprises a set of high.quality design decisions that provide benefits throughout the life cycle of the system.
標(biāo)簽： architecture decision oriented Quality
上傳時(shí)間： 2014-10-28
上傳用戶(hù)：love_stanford
This example implements a gameport translator on the PIC16C765. The firmware translates a gaming device plugged into the gameport to a USB gaming device. The firmware is set up to translate the DexxaTM eight-button gamepad. Changes to the firmware will be necessary for a different gaming device.
標(biāo)簽： implements translator translates gameport
上傳時(shí)間： 2015-04-26
上傳用戶(hù)：yyq123456789
DSP音頻處理示例The benefits of real-time analysis provided by DSP/BIOS are often required in programs that were engineered without it. When the program is not built from the ground up using the DSP/BIOS kernel and real-time analysis features, the lack of familiarity prevents engineers from reaping the benefits of this very powerful tool set, especially in the final stage of development when real-time analysis is needed most. This application note provides an example of the necessary steps required to utilize DSP/BIOS features in order to bring these solutions to bear in an existing application.
標(biāo)簽： DSP real-time benefits analysis
上傳時(shí)間： 2014-01-06
上傳用戶(hù)：003030
LVQ學(xué)習(xí)矢量化算法源程序 This directory contains code implementing the Learning vector quantization network. Source code may be found in LVQ.CPP. Sample training data is found in LVQ1.PAT. Sample test data is found in LVQTEST1.TST and LVQTEST2.TST. The LVQ program accepts input consisting of vectors and calculates the LVQ network weights. If a test set is specified, the winning neuron (class) for each neuron is identified and the Euclidean distance between the pattern and each neuron is reported. Output is directed to the screen.
標(biāo)簽： implementing quantization directory Learning
上傳時(shí)間： 2015-05-02
上傳用戶(hù)：hewenzhi
一個(gè)j2me游戲代碼，使用Jbuilder + Mobile set 編譯
上傳時(shí)間： 2015-05-03
上傳用戶(hù)：王小奇
This example program shows how to configure and use the A/D Converter of the following microcontroller: STMicroelectronics ST10F166 After configuring the A/D, the program reads the A/D result and outputs the converted value using the serial port. To run this program... Build the project (Project Menu, Build Target) Start the debugger (Debug Menu, Start/Stop Debug Session) View the Serial Window (View Menu, Serial Window #1) View the A/D converter peripheral (Peripheral Menu, A/D Converter) Run the program (Debug Menu, Go) A debug script (debug.ini) creates buttons that set different analog values in A/D channels. As the program runs, you will see the A/D input and output change. Other buttons create signals that generate sine wave or sawtooth patterns as analog inputs. µ Vision3 users may enable the built-in Logic Analyzer to view, measure and compare these input signals graphically.
標(biāo)簽： microcontroll Converter configure following
上傳時(shí)間： 2014-12-01
上傳用戶(hù)：獨(dú)孤求源
This book focuses primarily on XML itself. It covers the fundamental rules that all XML documents and authors must adhere to, whether a web designer uses SMIL to add animations to web pages or a C++ programmer uses SOAP to exchange serialized objects with a remote database. This book also covers generic supporting technologies that have been layered on top of XML and are used across a wide range of XML applications.
標(biāo)簽： fundamental XML documents primarily
上傳時(shí)間： 2014-01-14
上傳用戶(hù)：zjf3110
Chipcon CC2420 reference design w/PA board rev B CC2420_w_PA_PCB.ZIP FABRICATION.PHO - fabrication drawing COPPER1.PHO - copper layer #1 (top side) COPPER2.PHO - copper layer #2 (inner ground plane) COPPER3.PHO - copper layer #3 (inner power plane) COPPER4.PHO - copper layer #4 (bottom side) TOPMASK.PHO - top side solder mask BOTTOMMASK.PHO - bottom side solder mask NCDRILL.DRL - drill data file NCDRILL.LST - drill list NCDRILL.REP - drill report
標(biāo)簽： 2420 FABRICATION reference fabricati
上傳時(shí)間： 2015-05-12
上傳用戶(hù)：xc216
VHDL 關(guān)于2DFFT設(shè)計(jì)程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.
標(biāo)簽： scinode1 scinode details 2DFFT
上傳時(shí)間： 2014-12-02
上傳用戶(hù)：15071087253
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