本文是基于Arria V和Cyclone V精度可調DSP模塊的高性能DSP應用與實現（英文資料）
上傳時間： 2013-10-27
上傳用戶：yzy6007
介紹了一種基于DSP和FPGA的磁鐵電源控制器的設計方案，闡述了該控制器硬件系統的組成，包括信號調理電路、中間數據處理部分、后端的驅動電路。同時給出了DSP和FPGA之間通過SPI接口通信的具體流程和輸出PWM波形死區部分的控制流程。設計的磁鐵電源控制器有很好的控制和運算能力，同時具有很好的靈活性和可靠性。
上傳時間： 2013-11-16
上傳用戶：1051290259
Alter FPGA的設計流程以及DSP設計.
上傳時間： 2013-11-07
上傳用戶：dudu1210004
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
上傳時間： 2013-11-16
上傳用戶：qingdou
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標簽： Spartan-XL Express XAPP FPGA
上傳時間： 2015-01-02
上傳用戶：nanxia
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間： 2013-11-01
上傳用戶：wojiaohs
Spartan-3AN 器件帶有可以用于儲存配置數據的片上Flash 存儲器。如果在您的設計中Flash 存儲器沒有與外部相連，那么Flash 存儲器無法從I/O 引腳讀取數據。由于Flash 存儲器在FPGA 內部，因此配置過程中Spartan-3AN 器件比特流處于隱藏狀態。這一配置成了設計安全的起點，因為無法直接從Flash 存儲器拷貝設計。
上傳時間： 2013-10-31
上傳用戶：R50974
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時間： 2013-10-21
上傳用戶：ligi201200
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
上傳時間： 2013-11-01
上傳用戶：hjkhjk
本白皮書主要介紹 Spartan®-6 FPGA 如何滿足大批量系統的需求。包括經濟高效地驅動商用存儲器芯片、構建芯片間的高性能接口、創新型節電模式，這些只是高性能、低功耗、低成本 Spartan-6 FPGA 解決諸多問題的一部分。
上傳時間： 2015-01-02
上傳用戶：jx_wwq
