The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs.
標(biāo)簽： TMS 320 fixed-point processor
上傳時(shí)間： 2013-12-27
上傳用戶：宋桃子
These instances, whenmapped to an N-dimensional space, represent a core set that can be used to construct an approximation to theminimumenclosing ball. Solving the SVMlearning problem on these core sets can produce a good approximation solution in very fast speed. For example, the core-vector machine [81] thus produced can learn an SVM for millions of data in seconds.
標(biāo)簽： N-dimensional whenmapped instances represent
上傳時(shí)間： 2016-11-23
上傳用戶：lixinxiang
This toolbox was designed as a teaching aid, which matlab is particularly good for since source code is relatively legible and simple to modify. However, it is still reasonably fast if used with the supplied optimiser. However, if you really want to speed things up you should consider compiling the matrix composition routine for H into a mex function. Then again if you really want to speed things up you probably shouldn t be using matlab anyway... Get hold of a dedicated C program once you understand the algorithm.
標(biāo)簽： particularly designed teaching toolbox
上傳時(shí)間： 2016-11-25
上傳用戶：hustfanenze
The XC226x derivatives are high-performance members of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize clock generation via PLL and internal or external clock sources. Onchip memory modules include program Flash, program RAM, and data RAM.
標(biāo)簽： high-performance full-feature derivatives Infineon
上傳時(shí)間： 2016-12-12
上傳用戶：wab1981
ucos2 is a file system for embedded applications which can be used on any media, for which you can provide basic hardware access functions. µ C/FS is a high performance library that has been optimized for minimum memory consumption in RAM and ROM, high speed and versatility. It is written in ANSI C and can be used on any CPU.
標(biāo)簽： which applications can for
上傳時(shí)間： 2017-01-04
上傳用戶：偷心的海盜
ucos2 is a file system for embedded applications which can be used on any media, for which you can provide basic hardware access functions. µ C/FS is a high performance library that has been optimized for minimum memory consumption in RAM and ROM, high speed and versatility. It is written in ANSI C and can be used on any CPU.
標(biāo)簽： which applications can for
上傳時(shí)間： 2017-01-04
上傳用戶：13517191407
GPS 接收程序 DEMO。 HsGpsDll Library 1.1 A GPS Control/Component for C/C++ HsGpsDll is a Windows Dynamic Link Library which provides access to any NMEA-183 compliant GPS receiver via a serial communications port. HsGpsDll is designed for use from Visual C, Visual Basic or other languages, capable of calling DLL functions. HsGpsDll allows a user application to read from a GPS device the current GPS position fix, velocity over ground (speed in kilometers per hour), plus number of of sattelites in view, current altitude (against mean sea level) and UTC date and time
標(biāo)簽： HsGpsDll GPS Component Control
上傳時(shí)間： 2014-07-17
上傳用戶：thuyenvinh
The Cyclone® III PCI development board provides a hardware platform for developing and prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a high-density of the memory to facilitate the design and development of FPGA designs which need huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
標(biāo)簽： development developing prototypi provides
上傳時(shí)間： 2017-01-29
上傳用戶：jjj0202
VC技術(shù)內(nèi)幕第五版,學(xué)習(xí)VC經(jīng)典書籍 The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet technologies and COM, which are key components of the new Windows Distributed interNet Application Architecture (DNA). In addition to supporting these platform initiatives, Visual C++ 6.0 also adds an amazing number of productivity-boosting features such as Edit And Continue, IntelliSense, AutoComplete, and code tips. These features take Visual C++ to a new level. We have tried to make sure that this book keeps you up to speed on the latest technologies being introduced into Visual C++.
標(biāo)簽： Microsoft continued Internet release
上傳時(shí)間： 2013-12-14
上傳用戶：ve3344
VHDL是由美國國防部為描述電子電路所開發(fā)的一種語言，其全稱為(Very High Speed Integrated Circuit) Hardware Description Language。 與另外一門硬件描述語言Verilog HDL相比，VHDL更善于描述高層的一些設(shè)計(jì)，包括系統(tǒng)級（算法、數(shù)據(jù)通路、控制）和行為級（寄存器傳輸級），而且VHDL具有設(shè)計(jì)重用、大型設(shè)計(jì)能力、可讀性強(qiáng)、易于編譯等優(yōu)點(diǎn)逐漸受到硬件設(shè)計(jì)者的青睞。但是，VHDL是一門語法相當(dāng)嚴(yán)格的語言，易學(xué)性差，特別是對于剛開始接觸VHDL的設(shè)計(jì)者而言，經(jīng)常會因某些小細(xì)節(jié)處理不當(dāng)導(dǎo)致綜合無法通過。為此本文就其中一些比較典型的問題展開探討，希望對初學(xué)者有所幫助，提高學(xué)習(xí)進(jìn)度。
上傳時(shí)間： 2017-02-18
上傳用戶：nanshan
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
