BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
標簽： compatible 300 Spartan2e BurchED
上傳時間： 2015-07-07
上傳用戶：star_in_rain
It can be use for low level Bank System Handling.
標簽： Handling System level Bank
上傳時間： 2013-12-21
上傳用戶：epson850
if an application works with restricted low level system calls, it must obtain a Microsoft Mobile2Market privileged signature. To get a privileged signature, logo certification is now a requirement, not an option! This article shows how to abstract some of the most common issues a developer will encounter when creating a native code application that must be logo certified for each platform. windowsmobile5.0以上版本logo注冊例子，可以加入自己的工程文件中。
標簽： application restricted Microsoft Mobile2Ma
上傳時間： 2017-01-16
上傳用戶：13160677563
Signal system and Matlab courses in the series of high-level programming and engineering applications
標簽： application engineering programming high-level
上傳時間： 2013-12-23
上傳用戶：netwolf
Mitigation of Non-linear Distortion Using PTS and IDAR Method for Multi-Level QAM-OFDM System
標簽： Multi-Level Mitigation Distortion Non-linear
上傳時間： 2014-11-26
上傳用戶：wff
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標簽： 4channel transla level 9519
上傳時間： 2013-11-19
上傳用戶：jisiwole
An implementation of the TCP/IP protocol suite for the LINUX operating system. INET is implemented using the BSD Socket interface as the means of communication with the user level.
標簽： implementation implemented the operating
上傳時間： 2015-02-25
上傳用戶：xuanjie
NORTi3 is a realtime multitasking operating system conforming to the micro-ITRON 3.0 specification. NORTi3 is divided into two packages: NORTi3 Standard and NORTi3 Extended. The product NORTi3 Extended has implemented all the system calls of level E placed as "added and extended functions” in the micro-ITRON specification as well as the system calls equivalent to level X.
標簽： specification multitasking micro-ITRON conforming
上傳時間： 2014-01-14
上傳用戶：saharawalker
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標簽： 8226 Programmable Compatible In-System
上傳時間： 2015-06-27
上傳用戶：dianxin61
