嵌入式CAN模塊 聯(lián)系 楊迪 15336417867 0531-55508458 QQ：1347978253 htp://www.easyele.cn CAN (Controller Area Network)即控制器局域網(wǎng)絡(luò),屬于工業(yè)現(xiàn)場總線的范疇。與一般的通信總線相比,CAN總線的數(shù)據(jù)通信具有突出的可靠性 、實(shí)時(shí)性和靈活性。嵌入式CAN模塊控制器功能強(qiáng)，通信效率高,是公認(rèn)的穩(wěn)定可靠的通訊模式，廣泛應(yīng)用于消防安防、智能樓宇、酒店門鎖、 煤礦通訊、船舶運(yùn)輸?shù)葢?yīng)用領(lǐng)域。本系統(tǒng)采汽車級(jí)CPU，更保障其穩(wěn)定性。客戶可以放心使用。 嵌入式CAN模塊 轉(zhuǎn) RS232 RS485 TTL ，可以幫助用戶快速實(shí)現(xiàn)具有CAN-bus通訊接口的儀器、儀表設(shè)備的項(xiàng)目設(shè)計(jì)，模塊集成了8bit微處理器 CAN控制器、CAN收發(fā)器、總線保護(hù)于一身，所有元器件布置在一個(gè)微型的封裝模塊之內(nèi)，用戶只需要知道RS232的通訊即可實(shí)現(xiàn)CAN通訊。客戶 可以方便使用。 在使用過程中，嵌入式CAN模塊可以工作于二種模式：透明傳輸模式和透明數(shù)據(jù)模式。并且提供上位機(jī)設(shè)計(jì)，UART輸出時(shí)可以為TTL電平，RS232 或RS485，對(duì)應(yīng)訂貨型號(hào)為 CAN-module-TTL / rs232 / 485。客戶應(yīng)注意。 嵌入式CAN模塊可以在CAN與RS232間精確的轉(zhuǎn)換信息，讓您更方便的通過PC或帶RS232端口的設(shè)備與CAN設(shè)備通訊。歡迎大家咨詢選購嵌入式CAN 模塊，是我公司自主研發(fā)生產(chǎn)，完全擁有知識(shí)產(chǎn)權(quán)，專業(yè)的產(chǎn)品包裝，詳細(xì)的資料光盤，性價(jià)比高，專業(yè)公司操作，及時(shí)的技術(shù)支持，完善的 售后服務(wù)，解決客戶的后顧之憂。
上傳時(shí)間： 2013-11-28
上傳用戶：13925096126
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽： switch Octal 9549 with
上傳時(shí)間： 2014-11-22
上傳用戶：xcy122677
The TRS232E is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/RS-232-Fvoltage levels from a single 5-V supply. Each receiver converts TIA/RS-232-F inputs to 5-V TTL/CMOS levels.This receiver has a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Eachdriver converts TTL/CMOS input levels into TIA/RS-232-F levels. The driver, receiver, and voltage-generatorfunctions are available as cells in the Texas Instruments LinASIC™ library.
標(biāo)簽： RECEIVER DRIVER DUAL 232
上傳時(shí)間： 2013-10-07
上傳用戶：waitingfy
82C54是專為Intel系列微處理機(jī)而設(shè)計(jì)的一種可編程時(shí)間間隔定時(shí)器/計(jì)數(shù)器，它是一種通用芯片，在系統(tǒng)軟件中可以把多級(jí)定時(shí)元素當(dāng)成輸入/輸出端口中的一個(gè)陣列看待。1. 與所有Intel系列兼容2. 操作速度高，與8MHz的8086、80186一起可實(shí)現(xiàn)“零等待狀態(tài)”的操作。3. 可處理從直流到10M頻率的輸入。4. 適應(yīng)性強(qiáng)5. 三個(gè)獨(dú)立的16位計(jì)數(shù)器6. 低功耗的CHMOS7. 與TTL完全兼容8. 6 種可編程的計(jì)數(shù)模式9. 以二進(jìn)制或BCD計(jì)數(shù)10. 狀態(tài)讀返回命令
標(biāo)簽： CHMOS 82C54 可編程 時(shí)間間隔
上傳時(shí)間： 2013-11-16
上傳用戶：elinuxzj
82C55A是高性能，工業(yè)標(biāo)準(zhǔn)，并行I/O的LSI外圍芯片；提供24條I/O腳線。 在三種主要的操作方式下分組進(jìn)行程序設(shè)計(jì)82C88A的幾個(gè)特點(diǎn)：(1)與所有Intel系列微處理器兼容；(2)有較高的操作速度；(3)24條可編程I/O腳線；(4)底功耗的CHMOS；(5)與TTL兼容；(6)擁有控制字讀回功能；（7）擁有直接置位/復(fù)位功能；（8）在所有I/O輸出端口有2.5mA DC驅(qū)動(dòng)能力；（9）適應(yīng)性強(qiáng)。方式0操作稱為簡單I/O操作，是指端口的信號(hào)線可工作在電平敏感輸入方式或鎖存輸出。所以，須將控制寄存器設(shè)計(jì)為：控制寄存器中:D7=1; D6 D5=00; D2=0。D7位為1代表一個(gè)有效的方式。通過對(duì)D4 D3 D1和D0的置位/復(fù)位來實(shí)現(xiàn)端口A及端口B是輸入或輸出。P56表2-1列出了操作方式0端口管腳功能。
上傳時(shí)間： 2013-10-26
上傳用戶：brilliantchen
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
標(biāo)簽： Bridge Memory Contr MPC
上傳時(shí)間： 2013-10-08
上傳用戶：18711024007
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽： C16x 微控制器 輸入信號(hào) 時(shí)序圖
上傳時(shí)間： 2014-04-02
上傳用戶：han_zh
7.1 并行接口概述并行接口和串行接口的結(jié)構(gòu)示意圖并行接口傳輸速率高，一般不要求固定格式，但不適合長距離數(shù)據(jù)傳輸7.2 可編程并行接口芯片82C55 7.2.1 8255的基本功能 8255具有2個(gè)獨(dú)立的8位I/O口（A口和B口）和2個(gè)獨(dú)立的4位I/O（C口上半部和C口下半部），提供TTL兼容的并行接口。作為輸入時(shí)提供三態(tài)緩沖器功能，作為輸出時(shí)提供數(shù)據(jù)鎖存功能。其中，A口具有雙向傳輸功能。8255有3種工作方式，方式0、方式1和方式2，能使用無條件、查詢和中斷等多種數(shù)據(jù)傳送方式完成CPU與I/O設(shè)備之間的數(shù)據(jù)交換。B口和C口的引腳具有達(dá)林頓復(fù)合晶體管驅(qū)動(dòng)能力，在1.5V時(shí)輸出1mA電流，適于作輸出端口。C口除用做數(shù)據(jù)口外，當(dāng)8255工作在方式1和方式2時(shí)，C口的部分引腳作為固定的聯(lián)絡(luò)信號(hào)線。
標(biāo)簽： 并行接口
上傳時(shí)間： 2013-10-25
上傳用戶：oooool
自制一臺(tái)ATMEL 89系列FLASH單片機(jī)編程器學(xué)習(xí)單片機(jī)最有用的恐怕是編程器和仿真機(jī),一臺(tái)商品化的編程器至少要幾百元,仿真機(jī)價(jià)格更高,往往讓初學(xué)者難以選擇。這里介紹的一款國外電子網(wǎng)站推出的廉價(jià)51編程器，能夠讀寫最常用的12種51單片機(jī)，自己動(dòng)手裝配一臺(tái)，既能鍛煉自己的動(dòng)手能力,又能廉價(jià)地裝備一臺(tái)多用編程器，無論是學(xué)習(xí)單片機(jī)或業(yè)余時(shí)間搞開發(fā)，都是一個(gè)非常好的選擇。筆者按照資料自制了一臺(tái)，十分好用，不敢獨(dú)享。特編譯了全部制作資料介紹給大家。這個(gè)編程器硬件使用標(biāo)準(zhǔn)的TTL系列器件而沒有使用特殊元件。它連接在計(jì)算機(jī)的并行端口，對(duì)PC的并口沒有特殊要求，所以配置很低的計(jì)算機(jī)也能用這個(gè)編程器。Atmel Flash 系列單片機(jī)是當(dāng)前最流行的單片機(jī)，易于擦寫，不象OTP芯片容易造成浪費(fèi)。特別是89系列單片機(jī)與大家熟悉的INTEL51系列單片機(jī)完全兼容，這個(gè)編程器支持的單片機(jī)主要是Atmel flash系列。支持的器件： 這個(gè)編程器支持以下ATMEL單片機(jī)AT89C51,AT89C52,AT89C55,AT89S51,AT89S52,AT89S53,AT89C51RC,AT89C55WD,AT89S8252,AT89C1051U,AT89C2051,AT89C4051注意：20腳的單片機(jī)需要一個(gè)簡單的適配器。（圖 2 ） 硬件： 圖1顯示了這個(gè)FLASH 編程器的電路圖，編程器和標(biāo)準(zhǔn)的計(jì)算機(jī)并口連接。電路圖中的U2是用于控制計(jì)算機(jī)和控制器之間的數(shù)據(jù)流，U4 鎖存低位地址字節(jié) ，U5 鎖存高位地址字節(jié) ，U3用于產(chǎn)生控制信號(hào)給被編程的單片機(jī)。IC U1用于產(chǎn)生編程脈沖給單片機(jī).當(dāng)U7提供編程電壓給控制器時(shí)，電源部分用U8產(chǎn)生邏輯5v供給。IC U6用于產(chǎn)生5V或6.5V VDD 電源電壓給單片機(jī)。
標(biāo)簽： ATMEL FLASH 單片機(jī)編程器
上傳時(shí)間： 2013-10-18
上傳用戶：bakdesec
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