This software designs the document management system may replace the tedious low effect the manual management, has used the c language programming, realized the document input to loan, the information management and the data compilation three big cores function
標(biāo)簽： the management software document
上傳時(shí)間： 2013-12-20
上傳用戶：yt1993410
c語言程序，將阿拉伯?dāng)?shù)字翻譯成英文。如輸入：792677321 輸出：seven hundred ninety-two million six hundred seventy-seven thousand three hundred twenty-one
上傳時(shí)間： 2014-01-03
上傳用戶：yyyyyyyyyy
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture selections that allow full customization of the generated model to the target application requirements.
標(biāo)簽： AccelWare generators introduce exercise
上傳時(shí)間： 2013-12-16
上傳用戶：2467478207
The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals: To support massive concurrency, on the order of tens of thousands of clients per node To exhibit robust performance under wide variations in load and, To simplify the design of complex Internet services. SEDA decomposes a complex, event-driven application into a set of stages connected by queues. This design avoids the high overhead associated with thread-based concurrency models, and decouples event and thread scheduling from application logic. SEDA enables services to be well-conditioned to load, preventing resources from being overcommitted when demand exceeds service capacity. Decomposing services into a set of stages also enables modularity and code reuse, as well as the development of debugging tools for complex event-driven applications.
標(biāo)簽： Event-Driven Architecture Internet building
上傳時(shí)間： 2015-09-28
上傳用戶：日光微瀾
Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
標(biāo)簽： representation Magnitude the magnitude
上傳時(shí)間： 2013-12-24
上傳用戶：金宜
The Engineering Vibration Toolbox is a set of educational programs written in Octave by Joseph C. Slater. Also included are a number of help files, demonstration examples, and data files containing raw experimental data. The codes include single degree of freedom response, response spectrum, finite elements, numerical integration, and phase plane analysis.
標(biāo)簽： C. Engineering educational Vibration
上傳時(shí)間： 2013-11-29
上傳用戶：jkhjkh1982
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
標(biāo)簽： integrating controller guidelines document
上傳時(shí)間： 2013-11-27
上傳用戶：電子世界
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
標(biāo)簽： integrating controller guidelines document
上傳時(shí)間： 2015-11-18
上傳用戶：xhz1993
A system simulation environment in Matlab/Simulink of RFID is constructed in this paper. Special attention is emphasized on the analog/RF circuit.Negative effects are concerned in the system model,such as phase noise of the local oscillator,TX-RX coupling,reflection of the environment, AWGN noise,DC offset,I/Q mismatch,etc.Performance of the whole system can be evaluated by changing the coding method,parameters of building blocks,and operation distance.Finally,some simulation results are presented in this paper.
標(biāo)簽： environment constructed simulation Simulink
上傳時(shí)間： 2014-01-09
上傳用戶：zhangliming420
TI 公司 三相交流電機(jī)矢量控制源程序，F(xiàn)24x ACI3_3 3-Phase Sensored Field Oriented Control (FOC)
上傳時(shí)間： 2013-12-20
上傳用戶：縹緲
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