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Tightly

  • LiteSQL is a C++ library that integrates C++ objects Tightly to relational database and thus provide

    LiteSQL is a C++ library that integrates C++ objects Tightly to relational database and thus provides an object persistence layer. LiteSQL supports SQLite3, PostgreSQL and MySQL as backends. LiteSQL creates tables, indexes and sequences to database and upgrades schema when needed.

    標簽: integrates relational database LiteSQL

    上傳時間: 2016-03-25

    上傳用戶:源弋弋

  • Using Tightly Coupled Memory with the Nios II Processor Tutorial

    Using Tightly Coupled Memory with the Nios II Processor Tutorial

    標簽: Processor Tutorial Tightly Coupled

    上傳時間: 2014-01-09

    上傳用戶:lvzhr

  • Wide-input dc/dc modules offer

    When a system designer specifies a nonisolated dc/dc powermodule, considering the needed input voltage range isequally as important as considering the required performanceattributes and features. Generally, nonisolated moduleshave either a narrow or a wide input voltage range. Narrowinputmodules typically have a nominal input voltage of3.3, 5, or 12 V. For systems that operate from a Tightlyregulated input bus—such as those that do not use batterybackup—a narrow-input module is often adequate sincethe input remains fairly stable.Offering greater flexibility, wide-input modules operatewithin a range of 7 to 36 V, which includes the popular12- or 24-V industrial bus. This enables a single module tobe used for generating multiple voltages. These modulesare ideal for industrial controls, HVAC systems, vehicles,medical instrumentation, and other applications that usea loosely regulated distribution bus. In addition, systemspowered by a rectifier/battery charger with lead-acidbattery backup almost always require wide-input modules.System designers who choose power supplies may wantto take a close look at the latest generation of wide-inputdc/dc modules.

    標簽: Wide-input modules offer dc

    上傳時間: 2014-12-24

    上傳用戶:dragonhaixm

  • 使用Nios II緊耦合存儲器教程

                 使用Nios II緊耦合存儲器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory  . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory  . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory  . . . . . . . . . . . 1–5

    標簽: Nios 耦合 存儲器 教程

    上傳時間: 2013-10-13

    上傳用戶:黃婷婷思密達

  • Computational+RFID

    Sensors are points ofcontact betweenthe material world ofatoms, mass, andenergy and the seemingly immaterial world of information, computation, and cognition. Linking these two domains more Tightly yields all sorts of practical benefits, such as improvedinputdevicesforcomputers,moreeffectivemedicaldevices(implantedor worn), more precise agricultural operations, better monitored buildings or bridges, more secure payment systems, and more reliable sensor–actuator control systems. There are many settings in which tighter coupling between digital and physical planes can enhance safety, security, performance, and reliability.

    標簽: Computational RFID

    上傳時間: 2020-06-08

    上傳用戶:shancjb

  • GD32F103數據手冊(英文)

    The GD32F103xx device is a 32-bit general-purpose microcontroller based on the ARM?Cortex?-M3 RISC core with best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex?-M3 is a next generation processor core whichis Tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.The GD32F103xx device incorporates the ARM ' Cortex?-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximumefficiency. It provides up to 3 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose

    標簽: gd32f103

    上傳時間: 2022-07-23

    上傳用戶:aben

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