This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
標(biāo)簽：
Tensilica
OpenCores
interface
the
上傳時(shí)間：
2013-12-21
上傳用戶：gonuiln
