全遙控6聲道AV機的匯編程序:;;;;;;;;;;;;;;;;;;;6CH AMPLIFIER;;;;;;;;;;;;;;;;;----腳位定義-----;;;;;;;;;;;;;;;;;;;6CH AMPLIFIER;;;;;;;;;;;;;;;;;----腳位定義----- PT6311_CLK EQU P3.4PT6311_STB EQU P3.5PT6311_DATA EQU P3.3 UP EQU P3.1DOEN EQU P3.0 PT2313_DATA EQU P0.7PT2313_CLK EQU P2.7 AC3 EQU P2.6 ;(控制4053的信號) M62429_DA EQU P2.3 ;(SURL/R)M62429_CK EQU P2.4 M62429_CK1 EQU P2.5 ;(C/BW) M62429_CK3 EQU P0.0 ;(ECHO,MVOL)M62429_DA3 EQU P1.7M_DELAY1 EQU P0.1M_DELAY2 EQU P0.2 AD_OUT BIT P0.5AD_IN BIT P0.6 ;----片內RAM定義--------GIF_SIGN EQU 40H ; 動畫進程標記(=1,走過場字幕 )GIF_TIME1 EQU 41H ; 動畫跑字的時間間隔速度GIF_LONG EQU 42H ; 動畫字幕的長度 DISP_BUFFER EQU 43H ; 顯示緩沖區地址指針DISP_INDEX EQU 44H ; PT6311片內地址指針
上傳時間： 2013-10-19
上傳用戶：fac1003
系統start-up 定時器• 為了讓振蕩器能夠穩定起振所需要的延時時間。• 其時間為1024 個振蕩器振蕩周期。制程和溫度漂移• 因RC 振蕩器的頻率與內建振蕩電容值有關，而此電容值與制程參數有關，所以不同的MCU 會表現出不一致性。在固定電壓和溫度下，振蕩頻率漂移范圍約±25%。• 對于同一顆MCU(與制程漂移無關)，其振蕩頻率會對工作電壓和工作溫度產生漂移。其對工作電壓和工作溫度所產生的漂移，可參考HOLTEK 網站上提供的相關資料。EMI/EMS(EMC)注意事項• ROSC 位置應盡量接近OSC1 引腳，其至OSC1 的連線應最短。• CS 可以提高振蕩器的抗干擾能力，其與MCU OSC1 和GND 的連線應最短。• RPU 在確定系統頻率之后，量產時建議不要接，因為其fSYS/4 頻率輸出會干擾到OSC1
上傳時間： 2014-01-20
上傳用戶：yyyyyyyyyy
典型的MCU/DSP/UP復位電源監控，外部看門狗專用電路。
上傳時間： 2013-10-11
上傳用戶：LANCE
The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating systems.
上傳時間： 2013-11-01
上傳用戶：ghostparker
CCStudio Platinum Edition is available in a number of ways. Existingcustomers who are up-to-date with their subscription service withTexas Instruments will receive their update automatically on a CD inthe mail. New customers who wish to purchase a copy of CCStudioPlatinum Edition can order TMDSCCSALL-1 starting May 23, 2005. A120-day Trial version will be also be available on CDROM startingJuly 11, 2005. Users may order the CDROM of the 120-day free copy
上傳時間： 2014-12-28
上傳用戶：gououo
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標簽： Solutions Analog Xilinx FPGAs
上傳時間： 2013-11-01
上傳用戶：a67818601
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
標簽： Solutions Analog Altera FPGAs
上傳時間： 2013-11-08
上傳用戶：蟲蟲蟲蟲蟲蟲
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上傳時間： 2013-11-15
上傳用戶：lyy1234
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
