General Design Specification:1. AC Input Range 180-264Vac, Isolated ac-dc offline, 12LEDS,Output 700mA2. Intelligent wall dimmer detections(Leading-edge dimmer , Trailing-edgedimmer , No-dimmer)3. Multiple dimming control scheme4. Wide dimming range from 1% up to 100%5. No visible flicker6. Resonant control to achieve high efficiency7. High Power Factor, 0.9 without dimmer8. Temperature degrade control to adjust the LED9. Primary-only Sensing eliminates opto-isolator feedback and simplifies design
標(biāo)簽： iw3617
上傳時間： 2021-12-03
上傳用戶：canderile
那么我們可以進(jìn)行如下計(jì)算：1，輸出電流Iout=Pout/Udc=600/400=1.5A2，最大輸入功率Pin=Pout/η=600/0.92=652W3，輸入電流最大有效值Iinrmsmax=Pin/Umin=652/85=7.67A4，那么輸入電流有效值峰值為Iinrmsmax*1.414=10.85A5，高頻紋波電流取輸入電流峰值的20%，那么Ihf=0.2*Iinrmsmax=0.2*10.85=2.17A6，那么輸入電感電流最大峰值為：ILpk=Iinrmsmax+0.5*Ihf=10.85+0.5*2.17=11.94A7，那么升壓電感最小值為Lmin=(0.25*Uout)/(Ihf*fs)=(0.25*400)/(2.17*65KHz)=709uH8，輸出電容最小值為：Cmin=Iout/(3.14*2*fac*Voutp-p)=1.5/(3.14*2*50*10)=477.7uF，實(shí)際電路中還要考慮hold up時間，所以電容容量可能需要重新按照hold up的時間要求來重新計(jì)算。實(shí)際的電路中，我用了1320uF，4只330uF的并聯(lián)。
標(biāo)簽： 變壓器
上傳時間： 2021-12-04
上傳用戶：
Texas instruments MIPI DSI to eDP converter. Input supports 2 channel, 4 lanes each, up to 1.5GBit/s. Total input bandwidth is 12Gbit/s. Output eDP 1.4 1,2 or 4 lanes up to 5.4Gbit/s. output up to 4096x2304 60fps.
上傳時間： 2021-12-22
上傳用戶：
一、設(shè)計(jì)目的1、學(xué)習(xí)基本理論在實(shí)踐中綜合運(yùn)用的初步經(jīng)驗(yàn)，掌握模擬電路設(shè)計(jì)的基本方法、設(shè)計(jì)步驟，培養(yǎng)綜合設(shè)計(jì)與調(diào)試能力。2、學(xué)會直流穩(wěn)壓電源的設(shè)計(jì)方法和性能指標(biāo)測試方法。3、培養(yǎng)實(shí)踐技能，提高分析和解決實(shí)際問題的能力。二、設(shè)計(jì)任務(wù)及要求1、設(shè)計(jì)一個連續(xù)可調(diào)的直流穩(wěn)壓電源，主要技術(shù)指標(biāo)要求：① 輸入（AC）：U=220V，f=50HZ；② 輸出直流電壓：U0=9→12v；③ 輸出電流：I0<=1A；④ 紋波電壓：Up-p<30mV；2、設(shè)計(jì)電路結(jié)構(gòu)，選擇電路元件，計(jì)算確定元件參數(shù)，畫出實(shí)用原理電路圖。3、自擬實(shí)驗(yàn)方法、步驟及數(shù)據(jù)表格，提出測試所需儀器及元器件的規(guī)格、數(shù)量。4、在實(shí)驗(yàn)室MultiSIM8-8330軟件上畫出電路圖，并仿真和調(diào)試，并測試其主要性能參數(shù)。
標(biāo)簽： 直流穩(wěn)壓電源
上傳時間： 2021-12-23
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標(biāo)簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
STM32L053C8T6數(shù)據(jù)手冊Features ? Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.27 μA Standby mode (2 wakeup pins) – 0.4 μA Stop mode (16 wakeup lines) – 0.8 μA Stop mode + RTC + 8 KB RAM retention – 139 μA/MHz Run mode at 32 MHz – 3.5 μs wakeup time (from RAM) – 5 μs wakeup time (from Flash) ? Core: ARM? 32-bit Cortex?-M0+ with MPU – From 32 kHz up to 32 MHz max. – 0.95 DMIPS/MHz ? Reset and supply management – Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) ? Clock sources – 1 to 25 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – High speed internal 16 MHz factory-trimmed RC (+/- 1%) – Internal low-power 37 kHz RC – Internal multispeed low-power 65 kHz to 4.2 MHz RC – PLL for CPU clock ? Pre-programmed bootloader – USART, SPI supported ? Development support – Serial wire debug supported ? Up to 51 fast I/Os (45 I/Os 5V tolerant) ? Memories – Up to 64 KB Flash with ECC – 8KB RAM – 2 KB of data EEPROM with ECC – 20-byte backup register
標(biāo)簽： stm32l053c8t6
上傳時間： 2022-02-06
上傳用戶：
The PW5410B is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 1.8V to 5V input with up to 100mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOUT) makethe PW5410B ideally suited for small, battery-powered applications
標(biāo)簽： pw5410
上傳時間： 2022-02-11
上傳用戶：wangshoupeng199
The PW5410A is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 2.7V to 5V input with up to 250mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOUT) makethe PW5410A ideally suited for small, battery-powered applications
標(biāo)簽： pw5410
上傳時間： 2022-02-11
上傳用戶：
The PW5200A/ PW5200C is high efficiency synchronous, PWM step-up DC/DC converters optimizedto provide a high efficient solution to medium power systems. The devices work with a 1.4MHz fixedfrequency switching. These features minimize overall solution footprint by allowing the use of tiny,low profile inductors and ceramic capacitors. Automatic PWM/PFM mode switching at light loadsaves power and improves efficiency
標(biāo)簽： pw5200
上傳時間： 2022-02-11
上傳用戶：
The PW4556 series of devices are highly integrated Li-Ion and Li-Pol linear chargers targetedat small capacity battery for portable applications. It is a complete constant-current/ constantvoltage linear charger. No external sense resistor is needed, and no blocking diode is required dueto the internal MOSFET architecture. It can deliver up to 300mA of charge current (using a goodthermal PCB layout) with a final float voltage accuracy of ±1%. The charge voltage is fixed at 4.2V or4.35V, and the charge current can be programmed externally with a single resistor. The chargerfunction has high accuracy current and voltage regulation loops and charge termination
標(biāo)簽： pw4556
上傳時間： 2022-02-11
上傳用戶：1208020161
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