In this paper, we discuss efficient coding and design styles using VeriLog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
本文簡單討論并總結了VHDL、VeriLog，System VeriLog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
One of the most misunderstood constructs in the VeriLog language is the nonblockingassignment. Even very experienced VeriLog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant VeriLog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how VeriLog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid VeriLog simulation race conditions
