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Verilog語言

結合XILINXCPLD所做的模擬RS232通信verilog源程序

結合XILINXCPLD所做的模擬RS232通信verilog源程序

標簽： XILINXCPLD verilog 232 RS

上傳時間： 2013-09-03

上傳用戶：gps6888
一段控制1394芯片的cpld的verilog程序

這是一段控制1394芯片的cpld的verilog程序,可以參考,在實際項目中已經采用.

標簽： verilog 1394 cpld 控制

上傳時間： 2013-09-04

上傳用戶：pkkkkp
i2c code for the verilog

i2c code for the verilog

標簽： verilog code i2c for

上傳時間： 2013-09-04

上傳用戶：DXM35
Cadence guide for verilog

Cadence guide for verilog

標簽： Cadence verilog guide for

上傳時間： 2013-09-04

上傳用戶：123454
以verilog HDL 語言編寫的一首歌曲

以verilog HDL 語言編寫的一首歌曲，可供初學者借鑒

標簽： verilog HDL 語言編寫

上傳時間： 2013-09-05

上傳用戶：wyiman
VERILOG HDL 實際工控項目源碼

VERILOG HDL 實際工控項目源碼\r\n開發工具 altera quartus2

標簽： VERILOG HDL 工控項目

上傳時間： 2013-09-05

上傳用戶：youmo81
Cadence Verilog Language and Simulation

Cadence Verilog Language and Simulation

標簽： Simulation Language Cadence Verilog

上傳時間： 2013-09-06

上傳用戶：yl1140vista
Verilog Coding Style for Efficient Digital Design

In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

標簽： Efficient Verilog Digital Coding

上傳時間： 2013-11-22

上傳用戶：han_zh
VHDL,Verilog,System verilog比較

本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

標簽： Verilog verilog System VHDL

上傳時間： 2013-10-16

上傳用戶：牛布牛
Verilog編碼中的非阻塞性賦值

One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

標簽： Verilog 編碼非阻塞性賦值

上傳時間： 2013-10-17

上傳用戶：tb_6877751