VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
標(biāo)簽： high implementation resolution algorithm
上傳時間： 2013-12-26
上傳用戶：yuchunhai1990
GOOD DIODE FOR HIGH SPEED SWITCHING
標(biāo)簽： SWITCHING DIODE SPEED GOOD
上傳時間： 2017-07-30
上傳用戶：hongmo
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
標(biāo)簽： HIGH-SPEED CONTROLLER DUAL-ROLE ON-THE-GO
上傳時間： 2017-08-01
上傳用戶：rocwangdp
High Speed Digital PCB Design by Mick Grant
標(biāo)簽： Digital Design Grant Speed
上傳時間： 2013-12-24
上傳用戶：a673761058
Wave resistance for high-speed catamarans.rar
標(biāo)簽： resistance catamarans high-speed Wave
上傳時間： 2014-06-02
上傳用戶：ghostparker
Cypress - EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller
標(biāo)簽： Microcontroller Controller High-Speed Peripheral
上傳時間： 2017-08-15
上傳用戶：ippler8
Supplemental information for a high-speed serial bus that integrates well with most IEEE standard 32-bit and 64-bit parallel buses is specified. It is intended to extend the usefulness of a low-cost interconnect between external peripherals, IEEE Std 1394-1995. This standard follows the ISO/IEC 13213:1994 Command and Status Register (CSR) architecture.
標(biāo)簽： Supplemental information high-speed integrates
上傳時間： 2014-03-07
上傳用戶：jjj0202
HIGH SPeed serdes designs and connectors and simulation models simulations used in signal Integrity and also has practical evaluation aof all connectors
上傳時間： 2015-04-09
上傳用戶：1234wei
EIA（ELECTRONIC INDUSTRIES ALLIANCE）標(biāo)準(zhǔn)文檔EIA-CEA-861-B，A DTV Profile for Uncompressed High Speed Digital Interfaces。
標(biāo)簽： ELECTRONIC INDUSTRIES ALLIANCE EIA-CEA
上傳時間： 2015-09-27
上傳用戶：hphh
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽： switch Octal 9549 with
上傳時間： 2014-11-22
上傳用戶：xcy122677
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