2012TI杯陜西賽題H題,2012TI杯陜西賽題B題--頻率補償電路.
上傳時間： 2013-10-07
上傳用戶：ysystc670
PSHLY-B回路電阻測試儀介紹
上傳時間： 2013-11-05
上傳用戶：木子葉1
針對目前使用的RS232接口數字化B超鍵盤存在PC主機啟動時不能設置BIOS，提出一種PS2鍵盤的設計方法。基于W78E052D單片機，采用8通道串行A/D轉換器設計了8個TGC電位器信息采集電路，電位器位置信息以鍵盤掃描碼序列形式發送，正交編碼器信號通過XC9536XL轉換為單片機可接收的中斷信號，軟件接收到中斷信息后等效處理成按鍵。結果表明，在滿足開機可設置BIOS同時，又可實現超聲特有功能，不需要專門設計驅動程序，接口簡單，成本低。 Abstract: Aiming at the problem of the digital ultrasonic diagnostic imaging system keyboard with RS232 interface currently used couldn?蒺t set the BIOS when the PC boot， this paper proposed a design method of PS2 keyboards. Based on W78E052D microcontroller，designed eight TGC potentiometers information acquisition circuit with 8-channel serial A/D converter， potentiometer position information sent out with keyboard scan code sequentially.The control circuit based on XC9536 CPLD is used for converting the mechanical actions of the encoders into the signals that can be identified by the MCU， software received interrupt information and equivalently treatmented as key. The results show that the BIOS can be set to meet the boot， ultrasound specific functionality can be achieved at the same time， it does not require specially designed driver，the interface is simple and low cost.
上傳時間： 2013-10-10
上傳用戶：asdfasdfd
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上傳時間： 2014-11-22
上傳用戶：xcy122677
The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽： High-speed transce 1042 TJA
上傳時間： 2014-12-28
上傳用戶：氣溫達上千萬的
The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽： High-speed transce 1051 TJA
上傳時間： 2013-10-17
上傳用戶：jisujeke
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
TKS仿真器B系列快速入門
上傳時間： 2013-10-31
上傳用戶：aix008
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
上傳時間： 2013-10-10
上傳用戶：geshaowei
一個簡單好用的B+樹算法實現
上傳時間： 2015-01-04
上傳用戶：縹緲
