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Very-<b>high-Speed</b>

  • High-speed Digital Design 中文版(高速數(shù)字設(shè)計)

    介紹高速電路的設(shè)計

    標簽: High-speed Digital Design 高速數(shù)字

    上傳時間: 2013-10-16

    上傳用戶:yt1993410

  • pci e PCB設(shè)計規(guī)范

    This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.  

    標簽: pci PCB 設(shè)計規(guī)范

    上傳時間: 2013-10-15

    上傳用戶:busterman

  • 基于IR2101最大功率跟蹤逆變器的設(shè)計

    為解決直流逆變交流的問題,有效地利用能源,讓電源輸出最大功率,設(shè)計了高性能的基于IR2101最大功率跟蹤逆變器,并以SPMC75F2413A單片機作為主控制器。高電壓、高速功率的MOSFET或IGBT驅(qū)動器IR2101采用高度集成的電平轉(zhuǎn)換技術(shù),同時上管采用外部自舉電容上電,能夠穩(wěn)定高效地驅(qū)動MOS管。該逆變器可以實現(xiàn)DC/AC的轉(zhuǎn)換,最大功率點的跟蹤等功能。實際測試結(jié)果表明,該逆變器系統(tǒng)具有跟蹤能力強,穩(wěn)定性高,反應(yīng)靈敏等特點,該逆變器不僅可應(yīng)用于普通的電源逆變系統(tǒng),而且可應(yīng)用于光伏并網(wǎng)發(fā)電的逆變系統(tǒng),具有廣泛的市場前景。 Abstract:  To solve the problem of DC-AC inverter, and to utilize solar energy more efficiently, the design of maximum power point tracking inverter based on IR2101 was achieved with a high-performance, which can make the system output power maximum. SPMC75F2413A was adopted as main controller. IR2101 is a high voltage, high speed power MOSFET and IGBT driver. It adopted highly integrated voltage level transforming technology, and an external bootstrap capacitor was used, which could drive MOS tube efficiently and stably. Many functions are achieved in the system, such as DC/AC conversion, maximun power point tracking, etc. The actual test result shows that the inverter system has characteristics of strong tracking ability, high stability and reacting quickly. The design can not only be used in ordinary power inverter system, but also be used in photovoltaic power inverter system. The design has certain marketing prospects

    標簽: 2101 IR 最大功率跟蹤 逆變器

    上傳時間: 2013-11-17

    上傳用戶:lliuhhui

  • C8051F020

    HIGH SPEED 8051 μC CORE - Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz System Clock - 22 Vectored Interrupt Sources MEMORY - 4352 Bytes Internal Data RAM (256 + 4k) - 64k Bytes In-System Programmable FLASH Program Memory - External Parallel Data Memory Interface – up to 5Mbytes/sec DIGITAL PERIPHERALS - 64 Port I/O; All are 5V tolerant - Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial Ports Available Concurrently - Programmable 16-bit Counter/Timer Array with 5 Capture/Compare Modules - 5 General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES - Internal Programmable Oscillator: 2-to-16MHz - External Oscillator: Crystal, RC, C, or Clock - Real-Time Clock Mode using Timer 3 or PCA SUPPLY VOLTAGE ........................ 2.7V to 3.6V - Typical Operating Current: 10mA @ 25MHz - Multiple Power Saving Sleep and Shutdown Modes 100-Pin TQFP (64-Pin Version Available) Temperature Range: –40°C to +85°C

    標簽: C8051F020

    上傳時間: 2013-10-12

    上傳用戶:lalalal

  • 單片直接驅(qū)動數(shù)碼管的計數(shù)器程序

      a_bit equ 20h ;個位數(shù)存放處   b_bit equ 21h ;十位數(shù)存放處   temp equ 22h ;計數(shù)器寄存器   star: mov temp,#0 ;初始化計數(shù)器   stlop: acall display   inc temp   mov a,temp   cjne a,#100,next ;=100重來   mov temp,#0   next: ljmp stlop   ;顯示子程序   display: mov a,temp ;將temp中的十六進制數(shù)轉(zhuǎn)換成10進制   mov b,#10 ;10進制/10=10進制   div ab   mov b_bit,a ;十位在a   mov a_bit,b ;個位在b   mov dptr,#numtab ;指定查表啟始地址   mov r0,#4   dpl1: mov r1,#250 ;顯示1000次   dplop: mov a,a_bit ;取個位數(shù)   MOVC A,@A+DPTR ;查個位數(shù)的7段代碼   mov p0,a ;送出個位的7段代碼

    標簽: 直接驅(qū)動 數(shù)碼管 計數(shù)器 程序

    上傳時間: 2013-11-06

    上傳用戶:lx9076

  • 基于AVR的新型防汽車追尾安全裝置設(shè)計

    針對目前汽車追尾事件頻發(fā)問題,提出一種防汽車車前和車后追尾的安全裝置設(shè)計。該設(shè)計以高性能、低功耗的8位AVR微處理器ATmega8L為核心,結(jié)合霍爾式車速傳感器、激光雷達測距裝置和MMA7260QT加速度傳感器,能夠兼顧車前和車后,摒棄以往設(shè)計中只考慮車前或車后單一性缺點,尤其適用于高速、夜晚或新手行車。 Abstract:  Aiming at the high frequency of vehicle rear-end collision,a safe device design of anti-vehicle rear-end collision is presented.In the design,the high-performance,low-power8-bit AVR microprocessor ATmega8L is utilized as a core combined with Hall-type speed sensor,laser-radar ranging devices and the acceleration sensor MMA7260QT.The design considers both the front and back of a car,and overcomes the drawbacks of former designs in which only the front or the back of the car is considered,so it is especially suitable for high-speed,night or the beginner’s driving.

    標簽: AVR 汽車追尾 裝置

    上傳時間: 2013-10-14

    上傳用戶:GavinNeko

  • 基于C8051F320的心電監(jiān)護系統(tǒng)設(shè)計

    介紹一種基于C8051單片機的動態(tài)心電監(jiān)護系統(tǒng)。該系統(tǒng)由兩部分組成:以C8051F320單片機為核心的數(shù)據(jù)采集裝置和以PC機為平臺的分析處理系統(tǒng)。硬件電路功耗低,由單片機自帶的USB接口將數(shù)據(jù)傳送給PC機。軟件平臺采用LabVIEW可視化虛擬儀器系統(tǒng)開發(fā)平臺,將傳統(tǒng)儀器的功能模塊集成到計算機中,用戶可通過修改虛擬儀器的程序改變其功能。采用USB接口實時傳輸心電數(shù)據(jù),并將數(shù)據(jù)采集模塊設(shè)計為計算機外設(shè),使該系統(tǒng)高速快捷、小巧便攜。 Abstract:  In this design,a low-cost ECG electrocardiogram monitoring system is introduced,which consists of two parts:data acquisition device based on C8051F320and PC terminal as the analysis and processing system.The system is low-power consumption,the data is transmitted to the PC terminal by USB interface of the C8051F320.By using the visible virtual instrument system developing platform LabVIEW,the traditional instruments function modules are integrated into the computer,so the user can modify virtual instrument software to change its function to meet their needs.Using USB in-terface to realize real-time ECG data transmission,in addition,ECG data acquisition module is designed as the computer peripheral,which makes the syetem high-speed and portable.

    標簽: C8051F320 心電監(jiān)護 系統(tǒng)設(shè)計

    上傳時間: 2013-11-13

    上傳用戶:zhangzhenyu

  • 基于AVR單片機的USB接口設(shè)計

    以AVR單片機ATmega8和USB接口器件PDIUSBD12為核心,基于標準的USB1.1協(xié)議,設(shè)計一種通用USB接口模塊,以滿足嵌入式系統(tǒng)中對USB接口的需求。對模塊的硬件電路或單片機固件程序的硬件接口層稍加修改即可用于其他各種微處理器。該模塊可為各種嵌入式系統(tǒng)增加USB接口,實現(xiàn)與USB主機系統(tǒng)通信。 Abstract:  Based on AVR microcontroller ATmega8 and USB interface chip PDIUSBD12, a general USB interface module is designed according to USB1.1 protocol for various requirements of embedded systems. Only with few modifications in circuit or hardware abstract layer of firmware, the module can be used on many types of microprocessors. All kinds of embedded systems can realize high speed and stable communication with USB host systems, owing to the facility of this module.

    標簽: AVR USB 單片機 接口設(shè)計

    上傳時間: 2014-01-08

    上傳用戶:趙云興

  • 基于STC12C5408AD的記憶示波器

    主要介紹構(gòu)成記憶示波器的STC12C5408AD增強型單片機8通道10位模數(shù)轉(zhuǎn)換功能的設(shè)置、應(yīng)用和具體的匯編程序設(shè)計,以及PC機串行通訊和圖形顯示的高速匯編程序的設(shè)計要點,并列舉實例說明其應(yīng)用效果。 Abstract:  The configuration, applications and the designs for? compiling program of the memorial oscillograph of 10 bits A/D conversation are introduced. It’s bases on STC12C5408AD 8? channels? single-chip? computer? in? enhancement? mode. It also recommends the devising essentials of high speed compiling program for PC serial communication and graphics display, lists examples to explain its effects in using.

    標簽: C5408 5408 STC 12C

    上傳時間: 2013-10-10

    上傳用戶:adada

  • lpc2478完全使用手冊

    NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.

    標簽: 2478 lpc 使用手冊

    上傳時間: 2013-11-15

    上傳用戶:zouxinwang

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