Interleaved Block address generator (customized block size and interleaving strip size).
標簽： size interleaving Interleaved customized
上傳時間： 2014-11-28
上傳用戶：ardager
spi slave 8bit address 1bit r/w 7bit number data
上傳時間： 2017-08-16
上傳用戶：ynzfm
這是用C語言寫的結合TC圖形庫寫出來的貪吃蛇，大家可以從中學習學習~~~ 運行時別忘了修改初始化圖形的地址：initgraph(&driver,&mode,address); 比如說我的 address=D:\Win-TC\projects， 因為要有EGAVGA.BGI圖形文件支持才能正常運行
上傳時間： 2013-06-10
上傳用戶：zgu489
·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver
標簽： nbsp SystemVerilog Design for
上傳時間： 2013-07-14
上傳用戶：ainimao
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
Switching regulators are of universal interest. LinearTechnology has made a major effort to address this topic.A catalog of circuits has been compiled so that a designengineer can swiftly determine which converter type isbest. This catalog serves as a visual index to be browsedthrough for a specific or general interest.
標簽： Collection Switching Regulator Circuit
上傳時間： 2013-11-09
上傳用戶：mh_zhaohy
Providing power for the Pentium® microprocessor family isnot a trivial task by any means. In an effort to simplify thistask we have developed a new switching regulator controlcircuit and a new linear regulator to address the needs ofthese processors. Considerable time has been spent developingan optimized decoupling network. Here are severalcircuits using the new LTC®1266 synchronous buck regulatorcontrol chip and the LT®1584 linear regulator toprovide power for Pentium processors and Pentium VREprocessors. The Pentium processor has a supply requirementof 3.3V ±5%. The Pentium VRE processor requires3.500V ±100mV.
上傳時間： 2013-11-01
上傳用戶：名爵少年
This white paper raises some fundamental issues the design engineer should address before deciding upon a communication approach for a wireless network. As no universal wireless network solution exists, it should be custom tailored to suit the application demands. Defining your application communication characteristics is the key to ensure optimal communication reliability and resistance to interfering noise sources.
標簽： 無線通信網(wǎng)絡 基本概念
上傳時間： 2013-11-23
上傳用戶：zhichenglu
單片機作為一種微型計算機，其內部具有一定的存儲單元（8031除外），但由于其內部存儲單元及端口有限，很多情況下難以滿足實際需求。為此介紹一種新的擴展方法，將數(shù)據(jù)線與地址線合并使用，通過軟件控制的方法實現(xiàn)數(shù)據(jù)線與地址線功能的分時轉換，數(shù)據(jù)線不僅用于傳送數(shù)據(jù)信號，還可作為地址線、控制線，用于傳送地址信號和控制信號，從而實現(xiàn)單片機與存儲器件的有效連接。以單片機片外256KB數(shù)據(jù)存儲空間的擴展為例，通過該擴展方法，僅用10個I/O端口便可實現(xiàn)，與傳統(tǒng)的擴展方法相比，可節(jié)約8個I/O端口。 Abstract: As a micro-computer,the SCM internal memory has a certain units(except8031),but because of its internal storage units and the ports are limited,in many cases it can not meet the actual demand.So we introduced a new extension method,the data line and address lines combined through software-controlled approach to realize the time-conversion functions of data lines and address lines,so the data lines not only transmited data signals,but also served as address lines and control lines to transmit address signals and control signals,in order to achieve an effective connection of microcontroller and memory chips.Take microcontroller chip with256KB of data storage space expansion as example,through this extension method,with only10I/O ports it was achieved,compared with the traditional extension methods,this method saves8I/O ports.
標簽： 單片機 P0口 數(shù)據(jù)存儲器 擴展
上傳時間： 2014-12-26
上傳用戶：adada
1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
上傳時間： 2013-11-08
上傳用戶：laozhanshi111
