為提高電容測量精度，針對電容式傳感器的工作原理設(shè)計(jì)了基于PIC16LF874單片機(jī)電容測量模塊。簡單闡述了電容測量電路的應(yīng)用背景和國內(nèi)外研究現(xiàn)狀，介紹了美國Microchip公司PIC16LF874單片機(jī)的特性。電容式傳感器輸出的動(dòng)態(tài)微弱電容信號(hào)通過PS021型電容數(shù)字轉(zhuǎn)換器把模擬量數(shù)據(jù)轉(zhuǎn)換成數(shù)字量數(shù)據(jù)，所測數(shù)據(jù)由PIC16LF874單片機(jī)應(yīng)用程序進(jìn)行處理、顯示和保存。實(shí)驗(yàn)結(jié)果表明，固定電容標(biāo)稱值為10~20 pF 的測量值相對誤差在1%以內(nèi)，同時(shí)也可知被測電容容值越大，測量值和標(biāo)稱值相對誤差越小。 Abstract: To improve the accuracy of capacitance measurement，aimed at the principle of work of mercury capacitance acceleration transducer，the design of micro capacitance measurement circuit is based on the key PIC16LF874 chip. Briefly discusses the application of the capacitance measuring circuit for the background and status of foreign researchers，focusing on the United States PIC16LF874 microcontroller features. Capacitive sensor outputed signal through the dynamics of weak PS021-chip capacitors （capacitancedigital converter） to convert analog data into digital data，the measured data from the PIC16LF874 microcontroller application process， display and preservation. Experimental results show that the fixed capacitor 10pF ~ 20pF nominal value of the measured value of relative error is within 1%，but also it canbe seen the value of the measured capacitance larger，measuring value and the nominal value of relative error smaller.
上傳時(shí)間： 2013-10-29
上傳用戶：wojiaohs
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標(biāo)簽： Solutions Analog Xilinx FPGAs
上傳時(shí)間： 2013-11-01
上傳用戶：a67818601
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標(biāo)簽： Solutions Analog Xilinx FPGAs
上傳時(shí)間： 2013-11-07
上傳用戶：suicone
This example program shows how to configure and use the A/D Converter of the following microcontroller: STMicroelectronics ST10F166 After configuring the A/D, the program reads the A/D result and outputs the converted value using the serial port. To run this program... Build the project (Project Menu, Build Target) Start the debugger (Debug Menu, Start/Stop Debug Session) View the Serial Window (View Menu, Serial Window #1) View the A/D converter peripheral (Peripheral Menu, A/D Converter) Run the program (Debug Menu, Go) A debug script (debug.ini) creates buttons that set different analog values in A/D channels. As the program runs, you will see the A/D input and output change. Other buttons create signals that generate sine wave or sawtooth patterns as analog inputs. µ Vision3 users may enable the built-in Logic Analyzer to view, measure and compare these input signals graphically.
標(biāo)簽： microcontroll Converter configure following
上傳時(shí)間： 2014-12-01
上傳用戶：獨(dú)孤求源
在單片機(jī)應(yīng)用系統(tǒng)中，常用到模擬輸出，數(shù)模D/A轉(zhuǎn)換器（Digital to Analog Converter）是一種能把數(shù)字量轉(zhuǎn)換成模擬量的電子器件
標(biāo)簽： 單片機(jī) 應(yīng)用系統(tǒng)
上傳時(shí)間： 2016-04-11
上傳用戶：talenthn
This paper presents the key circuits of a 1MHz bandwidth, 750kb/s GMSK transmitter. The fractional-N synthesizer forming the basis of the transmitter uses a combined phasefrequency detector (PFD) and digital-to-analog converter (DAC) circuit element to obtain >28dB high frequency noise reduction when compared to classicalfrequency synthesis.
標(biāo)簽： fractional-N transmitter bandwidth circuits
上傳時(shí)間： 2016-04-14
上傳用戶：er1219
A few short years ago, the applications for video were somewhat confined—analog was used for broadcast and cable television, VCRs, set-top boxes, televisions and camcorders. Since then, there has been a tremendous and rapid conversion to digital video, mostly based on the MPEG-2 video compression standard. Today, in addition to the legacy DV, MPEG-1 and MPEG-2 audio and video com- pression standards, there are three new high- performance video compression standards. These new video codecs offer much higher video compression for a given level of video quality.
標(biāo)簽： applications for confined somewhat
上傳時(shí)間： 2016-10-29
上傳用戶：bjgaofei
This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.
標(biāo)簽： describes unisersal document phase-lo
上傳時(shí)間： 2014-01-13
上傳用戶：hustfanenze
this is a digital intercom projects using ADC PWM and UART interrupt. you take the value from mic enter it to ADC and then send serially to the other microcontroller which receives the data and transform the digital data into analog data by PWM which is connected to speaker
標(biāo)簽： interrupt intercom projects digital
上傳時(shí)間： 2017-04-19
上傳用戶：亞亞娟娟123
This article covers many of the fundamentals of analog video. Video is defined for our purposes here as "moving pictures." Still imaging, like what is found in digital still cameras or scanners, is not covered. The requirements for still imaging do have a lot in common with those for video, but the differences are significant enough to be dealt with as a separate discipline.
標(biāo)簽： fundamentals purposes article defined
上傳時(shí)間： 2013-12-17
上傳用戶：黑漆漆
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