The attached file for motion estimation algorithms using matlab
標簽： algorithms estimation attached motion
上傳時間： 2017-04-21
上傳用戶：wweqas
here i attached ARM processor related documents that will bevery useful to program in LPC2129.
標簽： documents processor attached related
上傳時間： 2017-05-16
上傳用戶：ZJX5201314
The zip file contais a sample program to check the sybase database connectivity. I ve attached the makefile as well for compilation on windows. Usage : test_conn <sybaseservername> <dbname> <username>
標簽： connectivity the attached database
上傳時間： 2017-06-28
上傳用戶：luke5347
the attached file contains artifitial neural network code
標簽： artifitial attached contains network
上傳時間： 2013-12-17
上傳用戶：小碼農lz
the attached file contains artifitial neural network code to solve xor
標簽： artifitial attached contains network
上傳時間： 2013-12-25
上傳用戶：hn891122
the attached file contains k means code using visual basic
標簽： attached contains visual basic
上傳時間： 2014-01-02
上傳用戶：firstbyte
the attached file contains backpropagation code using visual basic
標簽： backpropagation attached contains visual
上傳時間： 2013-11-28
上傳用戶：cainaifa
here i have attached C coding for LDPC decoder.
標簽： attached decoder coding here
上傳時間： 2017-08-14
上傳用戶：teddysha
Sample program on how to blink LEDs attached on PIC32 microcontroller I/O pins.
標簽： microcontroller attached program Sample
上傳時間： 2017-09-05
上傳用戶：rishian
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
