This document provides general hardware and layoutconsiderations and guidelines for hardware engineersimplementing a DDR3 memory subsystem.The rules and recommendations in this document serve as aninitial baseline for board designers to begin their specificimplementations, such as fly-by memory topology.
標(biāo)簽：
ddr3
上傳時(shí)間：
2021-11-21
上傳用戶：
