SAM9261 basicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches are disabled or enabled, with or without MMU and I Cache is disable or enabled, with or without MMU.
標(biāo)簽：
basicMMU
Example
project
9261
上傳時間：
2013-12-28
上傳用戶：zhanditian
