The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. I
The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. I...
beyond Compare技術(shù)資料
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?? beyond Compare全部資料 (127個)
these notes give an overview of beyond C to java and a good idea on how to develop applications in j
these notes give an overview of beyond C to java and a good idea on how to develop applications in j...
UCSC Kestrel and Beyond寫的一篇關(guān)于SIMD的講義,很好,很使用,也可以作為一個PPT模板使用的經(jīng)典例子哦
UCSC Kestrel and Beyond寫的一篇關(guān)于SIMD的講義,很好,很使用,也可以作為一個PPT模板使用的經(jīng)典例子哦...
compuete the fast fourier transformation of the image. it is very fast compare than fourier transfor
compuete the fast fourier transformation of the image. it is very fast compare than fourier transfor...
9、優(yōu)先級隊列 QueueNode.h Compare.h PriorityQueue.h Test.cpp 10、串 88 MyString.h MyString.cpp
9、優(yōu)先級隊列 QueueNode.h Compare.h PriorityQueue.h Test.cpp 10、串 88 MyString.h MyString.cpp ...
beyond conpare 綠色版
beyond conpare 綠色版，代碼對比工具...
基于FPGA的空時分組碼的設(shè)計與實現(xiàn)
隨著第三代移動通信系統(tǒng)(3G)向商業(yè)化的邁進(jìn)，以及超三代(Beyond 3G) 或被稱之為第四代(4G)移動通信系統(tǒng)的發(fā)展，對更高速率、更大容量和更好服務(wù)質(zhì)量的通信系統(tǒng)的需求正在不斷增長。另一方面，可...
Verilog Coding Style for Efficient Digital Design
In this paper, we discuss efficient coding and design styles using verilog. This can beim...
音頻數(shù)模轉(zhuǎn)換器DAC抖動的靈敏度分析
Abstract: This application note describes how sampling clock jitter (time interval error or "...
將您的微控制器ADC升級至真正的12位性能
Many 8-bit and 16-bit microcontrollers feature 10-bitinternal ADCs. A few include 12-bit ...