This paper examines the asymptotic (large sample) performance of a family of non-data aided feedforward (NDA FF) nonlinear least-squares (NLS) type carrier frequency estimators for burst-mode phase shift keying (PSK) modulations transmitted through AWGN and flat Ricean-fading channels. The asymptotic performance of these estimators is established in closed-form expression and compared with the modified Cram`er-Rao bound (MCRB). A best linear unbiased estimator (BLUE), which exhibits the lowest asymptotic variance within the family of NDA FF NLS-type estimators, is also proposed.
標簽： performance asymptotic examines non-data
上傳時間： 2015-12-30
上傳用戶：225588
S29NS-J 128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit), 32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit), 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, burst Mode Flash Memories Data Sheet
上傳時間： 2014-01-01
上傳用戶：qoovoop
自相似、長相關業務的生成及TCP擁塞控制的研究 目前,Internet的規模日益增大,承載的業務種類也不斷增加.Internet已給人們的生活和工作帶來了巨大的利益和影響.21世紀是通信的世紀,是互連網的世紀.經過20多年的發展,Internet已經在全球取得巨大的成功.該文對自相似、長相關基本理論進行了研究,得出了生成自相似、長相關業務的方法,即通過重尾分布ON/OFF源的N-burst模型的聚合業務來生成自相似、長相關業務,使用國際上比較通用的仿真軟件NS-2來進行仿真.并基于此特征業務,對TCP性能進行分析.最后對TCP擁塞控制進行改進,以適合自相似、長相關的的網絡特性,提高網絡性能.
上傳時間： 2013-12-18
上傳用戶：yxgi5
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
標簽： Tensilica OpenCores interface the
上傳時間： 2013-12-21
上傳用戶：gonuiln
#define RF_CHANNEL 25 // 2.4 GHz RF channel // BasicRF address definitions μ??·?¨ò? #define PAN_ID 0x2007 #define TX_ADDR 0xBEEF #define RX_ADDR 0x2520 // transmit data ′?ê?êy?Y #define APP_PAYLOAD_LENGTH 1 //ó|ó?3ìDò?o??3¤?è #define MAX_PAYLOAD_LENGTH 104 #define PACKET_SIZE sizeof(perTestPacket_t) #define RSSI_AVG_WINDOW_SIZE 32 // Window size for RSSI moving average // burst Sizes #define burst_SIZE_1 1000 #define burst_SIZE_2 10000 #define burst_SIZE_3 100000 #define burst_SIZE_4 1000000
上傳時間： 2017-02-28
上傳用戶：DoubleM
There is a phenomenal burst of research activities in mobile cloud computing systems, which extends cloud computing functions, ser- vices, and results to the world of future mobile communications applications, and the paradigm of cloud computing and virtualization to mobile networks. Mobile applications demand greater resources and improved interactivity for better user experience.
標簽： Mobile Cloud Computing Systems
上傳時間： 2020-05-30
上傳用戶：shancjb
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter burst_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
