MISRA C compliance Matrix
標(biāo)簽： compliance Matrix MISRA
上傳時間： 2013-12-15
上傳用戶：wendy15
MMC卡規(guī)范協(xié)議（英)完整版,包括MFG compliance,SPEC,MMCA030915-Taipei三類文檔,為pdf格式.
標(biāo)簽： compliance 030915 Taipei SPEC
上傳時間： 2016-02-17
上傳用戶：youmo81
DisplayPort-HDCP Specification compliance Test Specification
標(biāo)簽： Specification DisplayPort-HDCP compliance Test
上傳時間： 2013-12-08
上傳用戶：Ants
Full compliance with the USB Specification v1.1 and USB CDC v1.1 Support the RS232 Serial interface Support automatic handshake mode Support Remote wake-up and power management 256 bytes buffer each for upstream and downstream data flow Support default ROM or external EEPROM for device configuration On chip USB transceiver On chip crystal oscillator running at 12M Hz Supports Windows 98/SE, ME, 2000, XP, Windows CE3.0, CE .NET, Linux, and Mac OS 28 Pins SOIC package 28
標(biāo)簽： Specification compliance 1.1 USB
上傳時間： 2016-08-21
上傳用戶：dapangxie
Universal Serial Bus Mass Storage Class compliance Test Specification
標(biāo)簽： Specification compliance Universal Storage
上傳時間： 2014-01-21
上傳用戶：kernaling
USB Type-C Connectors and Cable Assemblies compliance Document Revision 2.1b 2021 國外網(wǎng)站下載的最新type-c 快充資料，分享一下
上傳時間： 2021-11-14
上傳用戶：kingwide
PCB電路設(shè)計(jì)中EMC兼容的討論 國外原版書籍 影印版
標(biāo)簽： compliance Design PCB EMC
上傳時間： 2013-05-17
上傳用戶：Zxcvbnm
PCI ExpressTM Architecture Add-in Card compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標(biāo)簽： Architecture ExpressTM PCI
上傳時間： 2013-11-03
上傳用戶：gy592333
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時間： 2013-10-15
上傳用戶：busterman
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上傳時間： 2013-11-12
上傳用戶：q123321
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