An easy, yet highly-configurable iptables-based firewall solution designed for everybody from home users to network admins. Functionality for IPv6, tunneling, IPSec, and advanced routing is planned.
awesome is a highly configurable, next generation framework window manager for X. It is very fast, light, and extensible. It is primarily targeted at the power user, developer, and anyone dealing with everyday computing tasks who wants to have fine-grained control over a graphical environment.
The Embedded configurable Operating System (eCos)start-to-finish guide to eCos solution building. Additional open source tools are included to configure a complete embedded software development environment.
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
The PCF8578 is a low power CMOS1 LCD row and column driver, designed to drive dotmatrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has40 outputs, of which 24 are programmable and configurable for the following ratios ofrows/columns: 32¤8, 24¤16, 16¤24 or 8¤32. The PCF8578 can function as a stand-alone LCDcontroller and driver for use in small systems. For larger systems it can be used inconjunction with up to 32 PCF8579s for which it has been optimized. Together these twodevices form a general purpose LCD dot matrix driver chip set, capable of driving displaysof up to 40960 dots. The PCF8578 is compatible with most microcontrollers andcommunicates via a two-line bidirectional bus (I2C-bus). Communication overhead isminimized by a display RAM with auto-incremented addressing and display bankswitching.
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
* This a software code module for a time-of-day clock object.
* The clock may be fixed 12-hour, fixed 24-hour, or dynamically
* configurable between these two types. Clock data can be accessed
* as a binary number representing the number of minutes since midnight
* or a BCD number formatted according to the time-of-day description
* in the TIME module 0404x. The functions work with time-of-day values
* which conform to normally accepted clock values of 1:00 to
* 12:59 BCD / 0 to 719 binary for a 12-hour clock or clock values
* 00:00 to 23:59 BCD / 0 to 1439 binary for a 24-hour clock. On power-up
* the clock is 12:00 BCD / 0 binary for a 12-hour or dynamically
* configurable clock, or 00:00 BCD / 0 binary for a 24-hour clock.
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of
designs implemented in the configurable System Logic (CSL) portion of a Triscend device.
