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configure

PowerXR I2C通信時序

This article describes the procedure to configure and program EXAR Corporation’s PowerXR Digital Power devicesvia I2C interface. Details shown here apply to XRP7704/08/40 and XRP7713/14 devices and PowerArchitectsoftware version 3.00.

標簽： PowerXR I2C 通信時序

上傳時間： 2013-10-20

上傳用戶：tianyi223
CodeWarrior開發工具套件簡要說明

CodeWarrior Development Tool Suites are comprehensive integrated developmentenvironments (IDE) that provide a highly visual and automated framework toaccelerate the development of the most complex embedded applications. Acrossmost stages of the development cycle, we offer tools to help configure, debug andoptimize your design built on Freescale MPUs, MCUs, DSPs and DSCs. These toolsuites provide solutions to get your design up and running fast.

標簽： CodeWarrior 開發工具套件

上傳時間： 2013-11-07

上傳用戶：youlongjian0
VxWorks6.x中的ML403嵌入式開發平臺

The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.

標簽： VxWorks 403 ML 嵌入式

上傳時間： 2013-10-26

上傳用戶：agent
Nios II 系列處理器配置選項

Nios II 系列處理器配置選項:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.

標簽： Nios II 列處理器

上傳時間： 2015-01-01

上傳用戶：mahone
Virtex-5 GTP Transceiver Wizar

The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

標簽： Transceiver Virtex Wizar GTP

上傳時間： 2013-10-20

上傳用戶：dave520l
sheerdns is a master DNS server whose zone records are stored on a One-Record-Per-File bases. Becaus

sheerdns is a master DNS server whose zone records are stored on a One-Record-Per-File bases. Because of this, it is the simplest of any DNS to configure, the easiest to update, and the most efficient for networks that experience a lot of updates (for example master servers for dynamic IP address ranges). You never have to restart it; any updates are available immediately without having to notify the sheerdns process. 來源: http://freshmeat.net/projects/sheerdns/?topic_id=149 sheerdns是一個主DNS服務器，它的域記錄保存在一個One-Record-Per-File（每文件一個記錄）的庫中。因此，它是最簡單的DNS配制，最容易更新，對于有大量更新的網絡（如動態IP地址范圍的主服務器）來說它是最高效的。你不必重新啟動它，任何更新不用通知對應DNS進程就可以立即生效。

標簽： One-Record-Per-File sheerdns records Becaus

上傳時間： 2015-01-10

上傳用戶：wyc199288
gcj java applet的web browser 插件

gcj java applet的web browser 插件，可替代jre 安裝步驟: ./configure make make install

標簽： browser applet java gcj

上傳時間： 2014-12-02

上傳用戶：redmoons
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.

標簽： system-on-chip integrated designed reusable

上傳時間： 2013-12-20

上傳用戶：小眼睛LSL
如果已經安裝好了vobsub

如果已經安裝好了vobsub，就可以運用vobsub里面帶的字幕提取工具vsrip提取字幕。打開VobSub程序組,運行vobsub.configure,點擊Open來打開vts_01_0.ifo文件(此文件已經拷貝到硬盤上,無需從光盤上找),選定放置字幕文件的子目錄,點擊確定.提取完成之后會生成Vts_01_0.sub和vts_01_0.idx兩個字幕文件,若按照DVDrip的做法是在最終視頻文件生成之后,將字幕文件更名并與主體一致,但在此這個步驟被提前了,因為real格式文件的字幕是嵌入在畫面那的.我們需要做的是將vts_01_0.idx和vts_01_0.sub更名為vts_01_1.idx和vts_01_1.sub,與vts_01_1.vob同名.這樣才能進行制作時被vobsub自動調用同步嵌入字幕

標簽： vobsub

上傳時間： 2015-04-28

上傳用戶：wangdean1101
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simula

This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.

標簽： the Analyzer Compiler project

上傳時間： 2013-12-19

上傳用戶：Yukiseop