This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
在Multisim 10軟件環境下，設計一種由運算放大器構成的精確可控矩形波信號發生器，結合系統電路原理圖重點闡述了各參數指標的實現與測試方法。通過改變RC電路的電容充、放電路徑和時間常數實現了占空比和頻率的調節，通過多路開關投入不同數值的電容實現了頻段的調節，通過電壓取樣和同相放大電路實現了輸出電壓幅值的調節并提高了電路的帶負載能力，可作為頻率和幅值可調的方波信號發生器。Multisim 10仿真分析及應用電路測試結果表明，電路性能指標達到了設計要求。
Abstract:
Based on Multisim 10， this paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
Lachesis an IRCRPG combat engine written in a combination of C and C++. The combat engine is being written for a specific RPG, but most of the project should be useful to IRCRPGs in general. It includes a native interface to the IRC protocol to allow it to act as an IRC bot, for such uses as dice rolling and acting as a remote-controlled client (RPG NPC perhaps).
pdnMesh is an automatic mesh generator and solver for Finite Element problems. It will also do post-processing to generate contour plots and Postscript printouts. GUI support using GTK or MFC (Win32) is available. The problem definition can be done in any form and given to pdnMesh as an input data file. Drawing Exchange Format (DXF) files can be directly imported to pdnmesh. The quality and the coarseness of the mesh can be controlled by giving input parameters.
yright 2002 Cygnal Integrated Products, Inc. // // Filename: LIION_BC_MAIN.c // Target Device: 8051F300 // Created: 11 SEP 2002 // Created By: DKC // Tool chain: KEIL Eval C51 // // This is a stand alone battery charger for a Lithium ION battery. // It utilizes a buck converter, controlled by the on-chip 8-bit PWM, // to provide constant current followed by constant voltage battery charge.
ATmega8 taillight circuitAn assembly language program that generates 5 different static patterns with switching from pattern-to-pattern controlled by the depression of one push-button switch (S2).
機頂盒界面源代碼：
## Avoid the so-called SINGAPPL to be initialized at runtime
## Used when the tuner is controlled externally by I2C and
## the PIDs forced to some specific values.
