plc basic reading material for graduate deSign-related aspects of the English literature plc, plc introduce the basic knowledge of the literature
標(biāo)簽： plc deSign-related literature material
上傳時(shí)間： 2017-04-11
上傳用戶：nairui21
density evolution for LDPC codes design and some related documents
標(biāo)簽： evolution documents density related
上傳時(shí)間： 2016-01-13
上傳用戶：daguda
Space-Time Processing for CDMA Mobile Communications.Written for research students and design engineers, this book addresses many basic questions related to the use of space-time processing in CDMA-based third-generation systems
標(biāo)簽： Communications Space-Time Processing for
上傳時(shí)間： 2014-01-13
上傳用戶：cooran
this document is related to the orcad layout plus. this document is useful in understanding and starting the orcad pcb design tool layout plus.
標(biāo)簽： document this understanding related
上傳時(shí)間： 2017-06-02
上傳用戶：wys0120
The idea for this book was born during one of my project-related trips to the beautiful city of Hangzhou in China, where in the role of Chief Architect I had to guide a team of very young, very smart and extremely dedicated software developers and verification engineers. Soon it became clear that as eager as the team was to jump into the coding, it did not have any experience in system architecture and design and if I did not want to spend all my time in constant travel between San Francisco and Hangzhou, the only option was to groom a number of local junior architects. Logically, one of the first questions being asked by these carefully selected future architects was whether I could recommend a book or other learning material that could speed up the learning cycle. I could not. Of course, there were many books on various related topics, but many of them were too old and most of the updated information was either somewhere on the Internet dispersed between many sites and online magazines, or buried in my brain along with many years of experience of system architecture.
標(biāo)簽： Telecommunication Gateways System Design for
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
ESD is a crucial factor for integrated circuits and influences their quality and reliability. Today increasingly sensitive processes with deep sub micron structures are developed. The integration of more and more functionality on a single chip and saving of chip area is required. Integrated circuits become more susceptible to ESD/EOS related damages. However, the requirements on ESD robustness especially for automotive applications are increasing. ESD failures are very often the reason for redesigns. Much research has been conducted by semiconductor manufacturers on ESD robust design.
標(biāo)簽： Guidelines Design Basic ESD
上傳時(shí)間： 2020-06-05
上傳用戶：shancjb
Design with Operational Amplifiers and Analog Integrated Circuits –3rd Edition Design wit
標(biāo)簽： Operational Amplifiers Integrated Circuits
上傳時(shí)間： 2013-06-12
上傳用戶：tianjinfan
Design Compiler 2007。新版本擴(kuò)展了拓?fù)浼夹g(shù)，以加速采用先進(jìn)低功耗和測(cè)試技術(shù)的設(shè)計(jì)收斂，幫助設(shè)計(jì)人員提高生產(chǎn)效率和 IC 性能。
上傳時(shí)間： 2013-05-29
上傳用戶：yanqie
·Verilog HDL: A Guide to Digital Design and
標(biāo)簽： nbsp Verilog Digital Design
上傳時(shí)間： 2013-04-24
上傳用戶：誰(shuí)偷了我的麥兜
·Phase-Locked Loop Circuit Design
標(biāo)簽： nbsp Phase-Locked Circuit Design
上傳時(shí)間： 2013-04-24
上傳用戶：lhc9102
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
