code for am and dsb and ssb modulation and demodulatIOn
標(biāo)簽： and demodulatIOn modulation code
上傳時(shí)間： 2014-01-09
上傳用戶：er1219
Qpsk Modulation and demodulatIOn.
標(biāo)簽： demodulatIOn Modulation Qpsk and
上傳時(shí)間： 2014-01-24
上傳用戶：jqy_china
problem of blind demodulatIOn of multiuser information symbols in a high-rate code-division multiple-access (CDMA) network in the presence of both multiple-access interference (MAI) and intersymbol interference (ISI) is considered.
標(biāo)簽： code-division demodulatIOn information multiuser
上傳時(shí)間： 2014-01-13
上傳用戶：熊少鋒
Title : Implementation of quadrature modulation and demodulatIOn Design Object : By implementing quadrature modulation and demodulatIOn of analog signals in digital signal processing, students will have better understanding of sampling and frequency analysis of discrete-time signals. Design Content : Make a MATLAB function which performs quadrature modulation and demodulatIOn for a input signal with anti-aliasing filtering.
標(biāo)簽： Implementation demodulatIOn implementing modulation
上傳時(shí)間： 2013-12-09
上傳用戶：蠢蠢66
Implementing quadrature modulation and demodulatIOn of analog signals in digital signal processing, using MATLAB
標(biāo)簽： Implementing demodulatIOn quadrature modulation
上傳時(shí)間： 2013-12-20
上傳用戶：gmh1314
Generation and demodulatIOn of FM PM.doc
標(biāo)簽： demodulatIOn Generation and
上傳時(shí)間： 2013-12-28
上傳用戶：youlongjian0
OFDM simulation, demodulatIOn
標(biāo)簽： demodulatIOn simulation OFDM
上傳時(shí)間： 2014-01-18
上傳用戶：xaijhqx
Designing read/write device (RWD) units for industrial RF-Identification applications is strongly facilitated by the NXP Semiconductors HITAG Reader Chip HTRC110. All needed function blocks, like the antenna driver, modulator demodulator and antenna diagnosis unit, are integrated in the HTRC110. Therefore only a minimum number of additional passive components are required for a complete RWD. This Application Note describes how to design an industrial RF-Identification system with the HTRC110. The major focus is dimensioning of the antenna, all other external components including clock and power supply, as well as the demodulatIOn principle and its implementatio
上傳時(shí)間： 2013-10-22
上傳用戶：zhengjian
針對(duì)傳統(tǒng)集成電路（ASIC）功能固定、升級(jí)困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡(jiǎn)便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測(cè)試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulatIOn of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時(shí)間： 2013-11-06
上傳用戶：liu123
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulatIOn circuit was designed based on the analysis of QDPSK signal modulation-demodulatIOn principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulatIOn circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
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