AT91SAM7SE512 Boundary-Scan description files (BSD)for LQFP 128 and LFBGA 144 packages.
標(biāo)簽： Boundary-Scan description packages LFBGA
上傳時(shí)間： 2016-04-03
上傳用戶：zhliu007
AT91SAM7S64_TQ64_bsd.zip Boundary-Scan description file (BSD) for the AT91SAM7S64 in LQFP 64 package.
標(biāo)簽： 64 Boundary-Scan description SAM
上傳時(shí)間： 2013-12-19
上傳用戶：hasan2015
AT91SAM7S256_TQ64_bsd.zip Boundary-Scan description file (BSD) for the AT91SAM7S256 in LQFP 64 package.
標(biāo)簽： Boundary-Scan description 256 SAM
上傳時(shí)間： 2013-12-18
上傳用戶：libenshu01
Session description Protocol parse code
標(biāo)簽： description Protocol Session parse
上傳時(shí)間： 2014-01-05
上傳用戶：yd19890720
This example provides a description of how to set a communication with the bxCAN in loopback mode: - transmit and receive a standard data frame by polling at 100Kbit/S - transmit and receive an extended data frame with interrupt at 500Kbit/S - lit some LEDs depending of the program succeed or not
標(biāo)簽： communication description provides loopback
上傳時(shí)間： 2016-04-24
上傳用戶：frank1234
This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED
標(biāo)簽： description provides transfer example
上傳時(shí)間： 2016-04-24
上傳用戶：ecooo
BSDL description for Top-Level Entity TMS320F2812 --
標(biāo)簽： description Top-Level Entity F2812
上傳時(shí)間： 2013-12-24
上傳用戶：semi1981
BSDL description for Top-Level Entity TMS320F2812
標(biāo)簽： description Top-Level Entity F2812
上傳時(shí)間： 2014-01-07
上傳用戶：熊少鋒
* Module description: * This main control loop shell provides everything required for a basic uIP * application using the RTL8019AS NIC
標(biāo)簽： description everything provides required
上傳時(shí)間： 2014-01-01
上傳用戶：ANRAN
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
標(biāo)簽： description implements Creation Original
上傳時(shí)間： 2016-05-27
上傳用戶：1109003457
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
