Oreilly.J2EE.Design.Patterns，非常經典的關于J2EE模式的書籍
標簽： Patterns Oreilly Design EE
上傳時間： 2013-11-28
上傳用戶：924484786
Addison Wesley - Advanced Programming Language Design
標簽： Programming Advanced Language Addison
上傳時間： 2013-12-10
上傳用戶：tonyshao
Olympic clock circuit schematic design reference,maybe you just search it now,haha1
標簽： schematic reference Olympic circuit
上傳時間： 2016-03-16
上傳用戶：it男一枚
pci card refence design ,using powerpcb or pads open it .
標簽： powerpcb refence design using
上傳時間： 2016-03-16
上傳用戶：sk5201314
Circuit Design with VHDL 美國麻省理工學院的經典教材 而且最重要的是已經經過去保護的，可以復制，可以打印，給大家分享！
上傳時間： 2016-03-16
上傳用戶：啊颯颯大師的
《Neural Network Design》 Martin T. Hagan, Howard B. Demuth, Mark H. Beale 一書中相關matlab演示程序軟件包。對于學習很有參考。
上傳時間： 2016-03-19
上傳用戶：zhanditian
Mahafza B.R, Elsherbeni A.Z. - MATLAB Simulations for Radar Systems Design - 2004 對于雷達系統設計師來說這是一本難得的寶典
標簽： A.Z. Simulations Elsherbeni Mahafza
上傳時間： 2016-03-20
上傳用戶：pinksun9
THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
標簽： CONDITIONS WARRANTIES YOU PROVIDED
上傳時間： 2016-03-21
上傳用戶：1427796291
Database curriculum design, library system, had high marks, the first New Year gift
標簽： curriculum Database library design
上傳時間： 2016-03-23
上傳用戶：himbly
Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
標簽： Testbenches enabling integral process
上傳時間： 2016-03-24
上傳用戶：1109003457
